• 제목/요약/키워드: Data Architectures

검색결과 360건 처리시간 0.027초

Data anomaly detection and Data fusion based on Incremental Principal Component Analysis in Fog Computing

  • Yu, Xue-Yong;Guo, Xin-Hui
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제14권10호
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    • pp.3989-4006
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    • 2020
  • The intelligent agriculture monitoring is based on the perception and analysis of environmental data, which enables the monitoring of the production environment and the control of environmental regulation equipment. As the scale of the application continues to expand, a large amount of data will be generated from the perception layer and uploaded to the cloud service, which will bring challenges of insufficient bandwidth and processing capacity. A fog-based offline and real-time hybrid data analysis architecture was proposed in this paper, which combines offline and real-time analysis to enable real-time data processing on resource-constrained IoT devices. Furthermore, we propose a data process-ing algorithm based on the incremental principal component analysis, which can achieve data dimensionality reduction and update of principal components. We also introduce the concept of Squared Prediction Error (SPE) value and realize the abnormal detection of data through the combination of SPE value and data fusion algorithm. To ensure the accuracy and effectiveness of the algorithm, we design a regular-SPE hybrid model update strategy, which enables the principal component to be updated on demand when data anomalies are found. In addition, this strategy can significantly reduce resource consumption growth due to the data analysis architectures. Practical datasets-based simulations have confirmed that the proposed algorithm can perform data fusion and exception processing in real-time on resource-constrained devices; Our model update strategy can reduce the overall system resource consumption while ensuring the accuracy of the algorithm.

차량 엔디엔 네트워크 안에 데이터 폭증 현상 실험적 평가 (Experimental Evaluation of Data Broadcast Storm in Vehicular NDN)

  • 임헌국
    • 한국정보통신학회논문지
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    • 제25권7호
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    • pp.940-945
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    • 2021
  • NDN (Named Data Networking)과 같은 미래 네트워크 아키텍처는 현재 호스트 중심 네트워크 기술에서 정보 중심 네트워크 기술로 데이터를 전송할 수 있는 방식을 변경하기 위해 탄생하였다. 최근 Vehicular NDN을 커넥티드 차량을 포함한 스마트 차량의 통신 네트워크 기술에 접목하기 위한 많은 연구가 진행되고 있다. Vehicular NDN 환경에서 Interest/Data 패킷 브로드 캐스팅으로 인한 데이터 트래픽 폭증은 VNDN 기반 데이터 통신을 실현하기 위해 해결해야 할 매우 중요한 문제이다. 본 논문에서는 데이터 브로드캐스트 폭풍 현상이 얼마나 심각하게 발생하는지를 보여주기 위해 VNDN 네트워크에서 네트워크 사이즈, 차량 스피드, 인터레스트 패킷 발생 빈도수의 증가에 따른 데이터 패킷 사본 발생을 ndnSIM을 이용하여 실험하고 평가한다. VNDN 안에 커넥티드 차량 수 및 Interest 패킷 발생 빈도수의 증가에 따라 중복된 데이터 패킷 처리량도 증가함을 확인하였다.

다중 라우트 서버를 두는 확장된 가상랜 시스템 (An Extended Virtual LAM System Deploying Multiple Route Server)

  • 서주연;이미정
    • 한국정보과학회논문지:정보통신
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    • 제29권2호
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    • pp.117-128
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    • 2002
  • 가상랜은 물리적 위치에 관계없이 마치 하나의 LAN에 연결되어 있는 것처럼 통신할 수 있는 구조로 브로드캐스트 도메인을 제한하여 대역폭 낭비를 감소시키고 전체 네트워크의 효율을 증가시킨다. Newbridge사는 IP 서브넷의 주소를 가상랜과 매핑하여 ATM-LAN 스위치 망에서 3계층 가상랜을 구성하는 VIVID 시스템을 개발하였다. 이 시스템에서는 하나의 라우트 서버에서 주소 해석과 가상랜 구성 및 브로드캐스트 데이타 전송을 모두 담당하기 때문에 망의 규모가 커지게 되면 라우트 서버가 병목 지점이 될 수 있다. 이와 같은 문제점을 해결하기 위해 택할 수 있는 방법 중 한 가지는 다중의 라우트 서버를 두는 것이다. 본 논문은 VIVID 시스템에 여러 개의 라우트 서버를 두는 구조로서 유기적인 구조와 독립적인 구조 두 가지를 제시하고 시뮬레이션을 통하여 각 구조의 특성을 비교 분석하였다. 시뮬레이션 결과, 브로드캐스트 세션의 길이와 브로드캐스트 세션 내에서의 브로드캐스트 데이타 프레임 발생 간격 등에 의해 제시한 두 가지 모델의 성능이 변하게 되며, 확장성과 데이타 전송의 효율성 간에 서로 상쇄 효과가 있음을 볼 수 있었다.

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

  • Ituero, Pablo;Lopez-Vallejo, Marisa
    • ETRI Journal
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    • 제30권1호
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    • pp.113-128
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    • 2008
  • Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

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Development of a system architecture for an advanced autonomous underwater vehicle, ORCA

  • Choi, Hyun-Taek;Lee, Pan-Mook
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2004년도 ICCAS
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    • pp.1791-1796
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    • 2004
  • Recently, great improvements have been made in developing autonomous underwater vehicles (AUVs) using stateof- the-art technologies for various kinds of sophisticated underwater missions. To meet increasing demands posed on AUVs, a powerful on-board computer system and an accurate sensor system with an well-organized control system architecture are needed. In this paper, a new control system architecture is proposed for AUV, ORCA (Oceanic Reinforced Cruising Agent) which is being currently developed by Korea Research Institute of Ships and Ocean Engineering (KRISO). The proposed architecture uses a hybrid architecture that combines a hierarchical architecture and a behavior based control architecture with an evaluator for coordinating between the architectures. This paper also proposed a sensor fusion structure based on the definition of 4 categories of sensors called grouping and 5-step data processing procedure. The development of the AUV, ORCA involving the system architecture, vehicle layout, and hardware configuration of on-board system are described.

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향상된 재구성능력을 가진 고속 어레이 구조 (Fast Array Architecture with Improved Reconfigurability)

  • 이재익;김진상;조원경;김영수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.451-454
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    • 2004
  • The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.

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유한체상의 자원과 시간에 효율적인 다항식 곱셈기 (Resource and Delay Efficient Polynomial Multiplier over Finite Fields GF (2m))

  • 이건직
    • 디지털산업정보학회논문지
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    • 제16권2호
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    • pp.1-9
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    • 2020
  • Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

다양한 도메인 기능을 갖는 PAC 시스템 개발 (Development of Programmable Automation Controllers (PACs) having Multi-Domain Functionality)

  • 김경돈;이강주;김형내;오진식;김찬봉
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.250-253
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    • 2005
  • A Programmable Automation Controller (PAC) has been developed by Turbotek Co., Ltd. The developed system has multi-domain functionality-including sequence control, motion control and HMI- on a single platform. The PAC also has a common development platform for the design and integration of multi-domain automated systems. Since hardware of the developed system has modular architectures, performance and specification of the controller are determined by combination of specific modules. The developed system employs de facto standards such as OPC interface that allow users to easily exchange data as part of networked multi-vendor systems.

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A Study on the Applications using Open GIS Component

  • Kim, Kwang-Soo;Choi, Hae-Ock
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2002년도 Proceedings of International Symposium on Remote Sensing
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    • pp.850-853
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    • 2002
  • This paper described some applications using Open GIS Component that was called MapBase. There were 4 applications : KSDI(Korea Spatial Data Infrastructure) funded by MOIC(Ministry of Information and Communication), National Plants Resource Management System supported by Korea Forest Service, 7-Underground Facilities Management System of Cheongju funded by MOCT(Ministry of Construction and Transportation), and National Disaster Management System supported by MOGAHA(Ministry of Government Administration and Home Affairs. Because they wanted to access heterogeneous spatial database, it was necessary to select MapBase as their base methodology. The main feature of MapBase was component S/W which provided the interoperability and reusability among GIS applications as well as non-GIS information system through common specification. In this paper, we showed some applications' architectures and functions to increase understanding MapBase. That would help you to make application using MapBase.

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Protein Disorder Prediction Using Multilayer Perceptrons

  • Oh, Sang-Hoon
    • International Journal of Contents
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    • 제9권4호
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    • pp.11-15
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    • 2013
  • "Protein Folding Problem" is considered to be one of the "Great Challenges of Computer Science" and prediction of disordered protein is an important part of the protein folding problem. Machine learning models can predict the disordered structure of protein based on its characteristic of "learning from examples". Among many machine learning models, we investigate the possibility of multilayer perceptron (MLP) as the predictor of protein disorder. The investigation includes a single hidden layer MLP, multi hidden layer MLP and the hierarchical structure of MLP. Also, the target node cost function which deals with imbalanced data is used as training criteria of MLPs. Based on the investigation results, we insist that MLP should have deep architectures for performance improvement of protein disorder prediction.