• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.46-54
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• 2018

The Internet of Things (IoT) is an environment in which various devices provide services to users through communications. Because of the nature of the IoT, data are stored and distributed in heterogeneous information systems. In this situation, IoT end applications should be able to access data without having information on where the data are or what the type of storage is. This mechanism is called Service Discovery (SD). However, some problems arise, since the current SD architectures search for data in physical devices. First, turnaround time increases from searching for services based on physical location. Second, there is a need for a data structure to manage devices and services separately. These increase the administrator's service configuration complexity. As a result, the device-oriented SD structure is not suitable to the IoT. Therefore, we propose an SD structure called Name-based Service-centric Service Discovery (NSSD). NSSD provides name-based centralized SD and uses the IoT edge gateway as a cache server to speed up service discovery. Simulation results show that NSSD provides about twice the improvement in average turnaround time, compared to existing domain name system and distributed hash table SD architectures.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.1
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• pp.84-90
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• 2023

ASL estimation of public building is based on how appropriate the maximum age of the asset is derived based on the age record of the asset in the statistical data owned by public institutions. This is because we get a 'constrained' ASL by that number. And it is especially true because other studies have assumed that the building is an Iowa curve R3. Also, in this study, the survival rate is 1% as the threshold value at which the survival curve and the predictable life curve almost coincide. Rather than a theoretical basis, in the national statistical survey, the value of residual assets was recognized from the net value of 10% of the acquisition value when the average service life has elapsed, and 1% when doubling the average service life has elapsed. It is based on the setting mentioned above. The biggest constraint in fitting statistical data to the Iowa curve is that the maximum ASL is selected at R3 150%, and the 'constrained' ASL is calculated by the proportional expression on the assumption that the Iowa curve is followed. In like manner constraints were considered. First, the R3 disposal curve for the RCC(reinforced cement concrete) building was prepared according to the discarding method in the 2000 work, and it was jointly worked on with the National Statistical Office to secure the maximum amount of vintage data, but the lacking of sample size must be acknowledged. Even after that, the National Statistical Office and the Bank of Korea have been working on estimating the Iowa curve for each asset class in the I-O table. Another limitation is that the asset classification uses the broad classification of buildings as a subcategory. Second, if there were such assets with a lifespan of 115 years that were acquired in 1905 and disposed of in 2020, these discarded data would be omitted from this ASL calculation. Third, it is difficult to estimate the correct Iowa curve based on the stub-curve even if there is disposal data because Korea has a relatively shorter construction history, accumulated economic wealth since the 1980's. In other words, "constrained" ASL is an under-estimation of its ASL. Considering the fact that Korea was an economically developing country in the past and during rapid economic development, environmental factors such as asset accumulation and economic ability should be considered. Korea has a short period of accumulation of economic wealth, and the history of 'proper' architectures faithful to building regulations and principles is short and as a result, buildings 'not built properly' and 'proper' architectures are mixed. In this study, ASL of RCC public building was estimated at 70 years.

• Journal of the Korean Society of Systems Engineering
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• v.12 no.2
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• pp.101-114
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• 2016

A model-based systems engineering (MBSE) approach to implementing hardware-based network cybersecurity controls for APR1400 non-safety data network is presented in this work. The proposed design was developed by implementing packet filtering and deep packet inspection functions to control the unauthorized traffic and malicious contents. Denial-of-Service (DoS) attack was considered as a potential cybersecurity issue that may threaten the data availability and integrity of DCS gateway servers. Logical design architecture was developed to simulate the behavior of functions flow. HDL-based physical architecture was modelled and simulated using Xilinx ISE software to verify the design functionality. For effective modelling process, enhanced function flow block diagrams (EFFBDs) and schematic design based on FPGA technology were together developed and simulated to verify the performance and functional requirements of network security controls. Both logical and physical design architectures verified that hardware-based cybersecurity controls are capable to maintain the data availability and integrity. Further works focus on implementing the schematic design to an FPGA platform to accomplish the design verification and validation processes.

• International journal of advanced smart convergence
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• v.12 no.2
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• pp.47-55
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• 2023

The automotive industry is undergoing a paradigm shift due to the convergence of IT and rapid digital transformation. Various components, including embedded structures and systems with complex architectures that incorporate IC semiconductors, are being integrated and modularized. As a result, there has been a significant increase in vehicle defects, raising expectations for the quality of automotive parts. As more and more data is being accumulated, there is an active effort to go beyond traditional reliability analysis methods and apply machine learning models based on the accumulated big data. However, there are still not many cases where machine learning is used in product development to identify factors of defects in performance and durability of products and incorporate feedback into the design to improve product quality. In this paper, we applied a prediction algorithm to the defects of automotive door devices equipped with automatic responsive sensors, which are commonly installed in recent electric and hydrogen vehicles. To do so, we selected test items, built a measurement emulation system for data acquisition, and conducted comparative evaluations by applying different machine learning algorithms to the measured data. The results in terms of R² score were as follows: Ordinary multiple regression 0.96, Ridge regression 0.95, Lasso regression 0.89, Elastic regression 0.91.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.39-48
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• 2016

One of the major trends of automotive networking architecture is the introduction of automotive Ethernet. Ethernet is already used in single automotive applications (e.g. to connect high-data-rate sources as video cameras), it is expected that the ongoing standardization at IEEE (IEEE802.3bw - 100BASE-T1, respectively IEEE P802.3bp - 1000BASE-T1) will lead to a much broader adoption in future. Those applications will not be limited to simple point-to-point connections, but may affect Electric/Electronic(EE) Architectures as a whole. It is agreed that IP based traffic via Ethernet could be secured by application of well-established IP security protocols (e.g., IPSec, TLS) combined with additional components like, e.g., automotive firewall or IDS. In the case of safety and real-time related applications on resource constraint devices, the IP based communication is not the favorite option to be used with complicated and performance demanding TLS or IPSec. Those applications will be foreseeable incorporate Layer-2 based communication protocols as, e.g., currently standardized at IEEE[13]. The present paper reflects the state-of-the-art communication concepts with respect to security and identifies architectural challenges and potential solutions for future Ethernet Switch-based EE-Architectures. It also gives an overview and provide insights into the ongoing security relevant standardization activities concerning automotive Ethernet. Furthermore, the properties of non-automotive Ethernet security mechanisms as, e.g., IEEE 802.1AE aka. MACsec or 802.1X Port-based Network Access Control, will be evaluated and the applicability for automotive applications will be assessed.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• Journal of architectural history
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• v.16 no.1
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• pp.9-28
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• 2007

We investigated the changes in the species of the woods used for Korean ancient and historic architectures, which include prehistoric excavated relics and existing wooden buildings in South Korea. The species data were collected from various sources such as excavation and repair reports, journal papers, and a few unpublished documents. We divided the building Periods as Paleolithic, Neolitic, Bronze Ages, Iron Age/Three Kingdoms, Koryo, Joseon (early, middle, late) and modem periods. In prehistoric periods, hardwoods were major species. Oak (Quercus spp.) woods dominated (94 percent in average); the others (5%) were Juglans mandshurica, Platycarya strobilacea, Castanea crenata, and few softwoods(1%). During Iron Age and Three Kingdom periods, oaks remained as a major species (57%) and others Platycarya strobilacea(21%), Castanea crenata(13%), and Pinus spp. (6%). The oak woods decreased in Koryo period and they occupied only 1.1%. Instead of oaks, pine (Pinus spp., 71%) and Zelkova serrata (22%) dominated in Koryo. In early and middle Joseon periods, pine woods (73%) remain as a major species and the others were oaks (14%) and Zelkova serrata (9%). As late Joseon came, the pine woods occupied more than 88%. In the late 19th and early 20th centuries, a few boreal species such as larch (Larix spp.) and spruce (Picea spp.), which grow in cold area, were found. We believe they were transported from northern Korea. The existing buildings in Korea are mainly from Joseon period and a few from late Koryo periods. During these periods, pine woods were used for most buildings. For such reason, pine woods were known as 'representative materials for historic buildings'. but earlier times, broad-leaved trees, i.e., oak and Zelkova woods were major materials. The changes in building materials resulted from both climate and human impacts. The dry climate and disturbed forests induce more pines in the mountains. We also compared the wood qualities of the species and found that Zelkova woods were superior ones and deserved more planting for future demands in the repair for historic buildings.