• The Journal of the Acoustical Society of Korea
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• v.23 no.1
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• pp.54-60
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• 2004

In order to mitigate the problems in storage space and network bandwidth for the full CD quality audio, current digital audio is always restricted by sampling rate and bandwidth. This restriction normally results in low sample rate audio or calls for the data compression scheme such as MP3. However, they can only reproduce a lower frequency range than a regular CD quality because of the Nyquist sampling theory. Consequently they lose rich spatial information embedded in high frequency. The propose of this paper is to propose efficient high frequency enhancement of low sample rate audio using n adaptive filtering and DWT analysis and synthesis. The proposed algorithm uses the LMS adaptive algorithm to estimate the missing high frequency contents in DWT domain and it then reconstructs the spectrally enhanced audio by using the DWT synthesis procedure. Several experiments with real speech and audio are performed and compared with other algorithm. From the experimental results of spectrogram and sonic test, we confirm that the proposed algorithm outperforms the other algorithm and reasonably works well for the most of audio cases.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.87-94
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• 2005

In this paper a low-power DWT(Discrete Wavelet Transform) design technique is proposed. As basic low-pass filter for analysis bank, comb filter is utilized, and in order to improve frequency response for the comb filter, a fourth order polynomial is also proposed. Another filters are designed by using perfect reconstruction conditions. The lowpass filter coefficients of the analysis filter bank are optimized based on the cost function and perfect reconstruction condition. The number of the multiplications and MSE(Mean Squared Error) performance of the proposed DWT filter bank are compared with those of the JPEG2000 (9, 7) filter bank. It is shown that number of multiplications of the proposed filter bank are saved with 33.3%, and MSE values of the proposed filter bank are also superior to those of the JPEG2000 (9, 7) filter bank.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.150-151
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• 2014

높은 SOC(state-of-charge) 추정알고리즘의 성능을 위해서는 측정된 배터리 단자전압의 정확도가 요구된다. 그렇지만, 예기치 않은 에러로 인해 단자전압에 노이즈 성분이 추가될 경우 SOC 추정성능의 저하를 피할 수 없다. 그러므로, 본 논문에서는 이산 웨이블릿 변환(DWT;discrete wavelet transform)의 다해상도 분석(MRA;multi resolution analysis)의 디노이징(denoising)기법을 적용한 이차전지의 SOC 추정방법을 소개한다. MRA의 시간-주파수 분석을 통해 분해(decomposition)된 저주파 성분(approximation;$A_n$)과 고주파 성분(detail;$D_n$)중 노이즈에 관계된 $D_n$의 고주파 상세 계수(detail coefficient) $d_{j,k}$를 새로이 조정하고 이를 합성(synthesis)하여 디노이징을 마무리 한다. 확장 칼만필터(EKF;extended Kalman filter)의 비교 분석을 통해 제안된 방법의 타당성을 검증한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1053-1059
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• 2005

The computer generated hologram (CGH) designs and produces digital information for generating 3-D (3-Dimension) image using computer and software instead of optically-sensed hologram of light interference, and it can synthesis a virtual object which is physically not in existence. Since digital hologram includes an amount of data as can be seen at the process of digitization, it is necessary that the data representing digital hologram is reduced for storing, transmission, and processing. As the efforts that are to handle hologram with a type of digital information have been increased, various methods to compress digital hologram called by fringe pattern are groped. Suitable proposal is encoding of hologram. In this paper, we analyzed the properties of CGH using tools of frequency transform, assuming that a generated CGH is a 2D image by introducing DWT that is known as the better tool than DCT for frequency transform. The compression and reconstruction result which was extracted from the wavelet-based codecs illustrates that it has better properties for reconstruction at the maximum 2 times higher compression rate than the Previous researches of Yoshikawa[2] and Thomas[3].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of the Korean Geophysical Society
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• v.4 no.2
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• pp.113-120
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• 2001

The discrete wavelet transform(DWT) has potential as a tool for supplying discriminatory attributes with which to distinguish seismic events. The wavelet transform has the great advantage over the Fourier transform in being able to localize changes. In this study, a discrete wavelet transform is applied to seismic traces for identifying seismic events and picking of arrival times for first breaks and S-wave arrivals. The precise determination of arrival times can greatly improve the quality of a number of geophysical studies, such as velocity analysis, refraction seismic survey, seismic tomography, down-hole and cross-hole survey, and sonic logging, etc. provide precise determination of seismic velocities. Tests for picking of P- and S- wave arrival times with the wavelet transform method is conducted with synthetic seismic traces which have or do not have noises. The results show that this picking algorithm can be successfully applied to noisy traces. The first arrival can be precisely determined with the field data, too.