• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.19-23
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• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.37-44
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• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.225-226
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• 2007

In this paper, we present our study about the optimization of the block matching algorithm on a VLIW based DSP. The block matching algorithm is well known for its computational burden in motion picture encoding. As supposed to the previous researches where the optimization is achieved by optimizing SAD, the most heavy routine of the block matching, we optimize the block matching algorithm by applying software pipelining technique to the whole routine of the algorithm. Through experiments, the efficiency of the proposed optimization is verified.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

• The Journal of the Acoustical Society of Korea
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• v.23 no.5
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• pp.420-427
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• 2004

This paper presents real time implementation of 4kbps EHSX (Enhanced Harmonic Stochastic Excitation) speech coder that combines the harmonic vector excitation coding with time-separated transition coding. The harmonic vector excitation coding uses the harmonic excitation coding for voiced frames and used the vector excitation coding with the structure of analysis-by-synthesis for unvoiced frames, respectively. For transition frames mixed with voiced and unvoiced signal, we use the time-separated transition coding. In this paper. we present the optimization methods of implementation speech coder on the EMS320C6701/sup (R)/ DSP. To reduce the complex for real-time implementation. we perform the optimization method in algorithm by replacing the complex sinusoidal synthesis method with IFFT. and we apply fully pipelines hand assembly coding after converting it from floating source to fixed source. To generate a more efficient code. we also make use or the available EMS320C6701/sup (R)/ resources such as Fastest67x library and memory organization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1428-1436
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• 2000

An adaptive predistorter linearizer suitable for the DSP implementation is proposed. Predistortion is performed by the DSP instead of the analog predistorter. RLS algorithm is employed for the optimization process to minimize the errors between the predistorter and postdistorter output signals. Computer simulation results for our linearizer show good performance.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.78-83
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• 2000

Vocoders used in digital mobile phone adopt new improved algorithm to achieve better communication quality. Therefore the communication problem occurs between mobile phones using different vocoder algorithms. In this paper, the efficient implementation of 8kbps and 13kbps QCELP into one DSP chip to solve this problem is presented. We also describe the optimization method at each level, that is, algorithm-level, equation-level, and coding-level, to reduce the complexity for the QCELP vocoder algorithm implementation. The complexity in the codebook search-loop that is the main part for the QCELP algorithm complexity can be reduced about 50% by using these optimizations. The QCELP implementation with our DSP requires only 25 MIPS of computation for the 8kbps and 33 MIPS for the 13kbps ones. The DSP for our real-time implementation is a 16-bit fixed-point one specifically designed for vocoder applications and has a simple architecture compared to general-purpose ones in order to reduce the power consumption.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.7-9
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• 2002

본 논문에서는 DSP 코드 생성시 어드레스 인스트럭션의 개수를 최소화하기위한 효과적 인 어드레스 코드 생성 기법을 제안하였다. 기존의 방법에서는 코드 스케줄링이 수행된 다음에 어드레스 코드가 생성되었다. 본 논문에서는 코드 스케줄링과 어드레스 코드 생성을 결합하였고, 어드레스 인스트럭션의 개수를 줄이기 위한 효과적인 스케줄링 방법을 제안하였다. 실험결과는 최근 연구에[6,8] 비해 23.7% 크기의 향상을 보여주었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.104-105
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• 2010

H.264/AVC는 기존의 동영상 압축 표준안보다 훨씬 뛰어난 압축 효율을 보이나 상대적으로 높은 계산 복잡도를 보인다. 또한 최근 모바일 어플리케이션 및 DTV 등에서의 실시간 구현의 수요가 급증함에 따라 하드웨어 구현보다 상대적으로 flexible한 구조인 DSP 환경에서의 최적화 연구가 활발히 진행 중이다. 본 논문에서는 기존의 다중 참조 픽처 고속 움직임 보상 알고리즘에 대하여 DSP 환경에 맞게 구현 및 최적화를 통하여 실시간 구현 및 최적화 경향파악을 하고 있다. 수행된 DSP 최적화를 통하여 움직임 추정 평균 계산량을 픽셀 당 약 56.17%로 크게 감소시켰다.