• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.227-232
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• 2015

Nowadays, there are many innovative products in the pro-audio market thanks to advanced IT technology, DSP is very important technology to process high quality audio signal in SR(Sound Reinforcement) system. Digital audio technology that converged with IT technology can give new user-experience. In this paper, we present a new digital crossover system for active speakers using DSP and network technology. The prototype of crossover module consists of various audio process module such as filters, delay, phase controls and also it provides user to remote monitoring and remote control features by internet connection.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.359-364
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• 2004

In this paper, we implemented real-time speaker undependent speech recognizer that is robust in noise environment using DSP(Digital Signal Processor). Implemented system is composed of TMS320C32 that is floating-point DSP of Texas Instrument Inc. and CODEC for real-time speech input. Speech feature parameter of the speech recognizer used robust feature parameter in noise environment that is transformed feature space of MFCC(met frequency cepstral coefficient) using ICA(Independent Component Analysis) on behalf of MFCC. In recognition result in noise environment, we hew that recognition performance of ICA feature parameter is superior than that of MFCC.

• The Journal of the Acoustical Society of Korea
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• v.23 no.2
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• pp.117-124
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• 2004

In this paper, we have been implemented the QPSK-based underwater transmission systems using DSP in order to transmit the underwater image data. We have adopted a BDPA (Block Data Parallel Architecture) to control multiple DSPs used in the transmitter and receiver in order to transmit the image data in real-time. We also have developed GUI software in order to drive and to debug the implemanted system in real-time. We have executed open sea tests in order to analyze the performance of the implemented system at East Sea near Kosung in Kangwon-Do. As a result of these experiments, it has been demonstrated that 10 kbps image data can be received without errors at 30m and 80m depth points, while the distance between the transmitter and the receiver is up to 20m.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.5 no.1
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• pp.25-36
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• 2006

This paper discusses the implementation and performance evaluation of a DSP-based digital beamformer using the Texas Instrument TMSC6711 DSP processor for smart antenna applications. Two adaptive beamforming algorithms which served as the brain for the beamformer, the Normalized Least-Mean-Square (NLMS) and the Constant Modulus Algorithms (CMA) were embedded into the processor and evaluated. Result shows that the NLMS-based digital beamformer outperforms the CMA-based digital beamformer: 1)For NLMS algorithm, the antenna steers to the direction of the desired user even at low iteration value and the suppression level towards the interferer increases as the number of iteration increase. For CMA algorithm, the beam radiation pattern slowly steers to the desired user as the number of iteration increased, but at arate slower than NLMS algorithm and the sidelobe level is shown to increases as the number of iteration increase. 2) The NLMS algorithm has faster convergence than CMA algorithm and the error convergence for CMA algorithm sometimes is subject to misadjustment.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Investigative Magnetic Resonance Imaging
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• v.7 no.1
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• pp.12-21
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• 2003

Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.707-714
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• 2016

Active driving safety systems for vehicle, such as the front collision avoidance, lane departure warning, and lane change assistance, have been popular to be adopted to the compact car. For improving performance and competitive cost, FMCW radar has been researched to adopt a phased array or a multi-beam antenna, and to integrate the front and the side radar. In this paper we propose several efficient methods to implement the signal processing module of FMCW radar system using low cost DSP. The pulse width modulation (PWM) based analog conversion, the approximation of time-eating functions, and the adoption of vector-based computation, etc, are proposed and implemented. The implemented signal processing board shows the real-time performance of 1.4ms pulse repetition interval (PRI) with 1024pt-FFT. In real road we verify the radar performance under real-time constraints of 10Hz update time.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.58-67
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• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.