• International Journal of Highway Engineering
• /
• v.15 no.6
• /
• pp.41-47
• /
• 2013

PURPOSES : The purpose of this study is about noise which is generated from roads and is consist of irregular frequency variation from low frequency to various band. The existing methods of noise reduction are sound barrier that uses insulation material and absorbing material or have applied passive technology of noise reduction by devices. The total frequency band is needed to apply active noise control. METHODS : In this study applies to the field of road traffic environment, signal processing controller and various analog signal input/output, the amplifier module is based on parallel-core embedded processor designed. DSP performs the control algorithm of the road traffic noise. Noise sources in the open space performance of evaluation were applied. In this study, controller of active signal processor was designed based on the module of audio input/output and main controller of embedded process. The controller of active signal processor operates noise reduction algorithm and performance tests of noise reduction in inside and outside environment were executed. RESULTS : The signal processing controller with OMAP-L137 parallel-core processors as the center, DSP processors in the active control operations dealt with quickly. To maximize the operation speed of an object and ARM processor is external function keys and display for functions and evaluating the performance management system was designed for the purpose of the interface. Therefore the reduction of road traffic noise has established an electronic controller-based noise reduction. CONCLUSIONS : It is shown that noise reduction is effective in the case of pour tonal sound and complex tonal sound below 500Hz by appling to Fx-LMS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.6
• /
• pp.580-588
• /
• 2009

A Missile Warning Radar is an essential sensor for active protection system to detect antitank missile in all weather environments. This paper presents the design, development, and test results of L-band pulsed Doppler radar system for main battle tank. This radar system consists of 3 LRUs, which include antenna unit, transmitter and receiver unit and radar signal & data processing unit. The developed core technologies include the patch antenna, SSPA transmitter, coherent I/Q detector, DSP based Doppler FFT filter, adaptive CFAR, SIW tracking capability, and threat decision. The design performance of the developed radar system is verified through various ground fixed and moving vehicle test.

• The Journal of the Korea Contents Association
• /
• v.9 no.3
• /
• pp.39-48
• /
• 2009

The Spectrum Sensing technology is the core technology of the Cognitive Radio (CR) system that is one of the future wireless communication technologies. This is the technology that temporarily allocates the frequency bandwidth by scanning surrounding wireless environments to keep licensed terminals and search the unused frequency bandwidth. In this paper, we implement the efficient Spectrum Sensing methods based on CR technology in an embedded board. The DVB-H signal with the 6MHz bandwidth is used as the RF input signal. And we confirm the Spectrum Sensing result using Modified Periodogram Method, Welch's Method, SCF Method. And also, We examine the execution speed of each of detailed functions and the performance of Spectrum Sensing methods on TI320C6416 DSP board inserted in an embedded board.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.20 no.4
• /
• pp.562-568
• /
• 2010

Until now, the implementation of servo motor control units which is being applied in various industrial ares such as industrial system, office equipment, home appliance and robotics, used the MCU and DSC(or DSP). However, MCU and DSC have limitations of not being able to maximize control efficiency of the motor and the flexibility. Thus, in this paper, we propose and implemented the designing method for development of servo motor control IP based on FPGA which have a structure to make the best motor control efficiency and flexibility of control,

• Journal of Information Processing Systems
• /
• v.15 no.2
• /
• pp.374-385
• /
• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.12
• /
• pp.44-55
• /
• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Journal of the Korea Convergence Society
• /
• v.2 no.1
• /
• pp.7-13
• /
• 2011

Informations of multimedia centering in the images, are combined acoustic and letter, etc. Although the network advances and the capacity of the storage media extends, these huge informations will not be able to accommodate. From meaning which is like this, International standards for the compression and a multiplexing of image, acoustic and voice H261 where admits standard, JPEG, JBIG, MPEG-l, MPEG-2, MPEG-4 and H263, G series etc, are core techniques of multimedia. At initial step of the base technique which creates the base of like this multimedia service time, we developed the real-time MPEG-4 transmission systems to provides real-time MPEG-4 multimedia services. This system means becomes the base technique which hereafter is developed and is applied various system. This system Will be able to apply from a videoconference, a building protection system and a VOD video system to use the Internet. And, They, the image sensing, embedded linux, and MPEG4 software, will become sourceful technique to develop the different system.

• The Journal of the Acoustical Society of Korea
• /
• v.25 no.2
• /
• pp.61-71
• /
• 2006

An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.

• Smart Structures and Systems
• /
• v.3 no.1
• /
• pp.69-88
• /
• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.116-119
• /
• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.