• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.159-160
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• 2015

최근 초기 투자비용은 큰 반면 에너지 이용률은 낮은 UPS(Uninterruptible power supply)를 ESS(Energy storage system)로서 활용하는 하이브리드 ESS에 대한 관심이 커지고 있다. 하이브리드ESS는 비상시 중요부하에 공급할 최소 전력을 제외한 전력을 수요관리로 활용함으로써 UPS에 저장되어 있는 에너지를 비상전원 기능과 수요관리 기능으로 폭넓게 사용할 수 있는 시스템이다. 이 시스템을 구성하는 3개의 PCS를 통합 제어하기 위해 채택한 듀얼코어 기반의 고성능 MCU TMS320F28377D를 이용하면 많은 PWM, ADC포트는 물론 충분한 연산시간 확보가 가능하다. 본 논문에서는 제안하는 하이브리드 ESS의 구성에 대해 소개하고 사용된 제어기의 구조, 각 PCS들을 통합 제어하기 위해 사용한 듀얼코어 기반의 DSP TMS320F28377D에 대해 설명하고자 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.219-222
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• 2012

최근 얼굴검출에 관한 연구는 FPGA를 통한 H/W설계부터 DSP, GPU, ARM Core에 효율적인 S/W 설계까지 다양하게 연구되고 있다. 본 연구에서는 Multi-Core에 효과적인 얼굴검출 방법을 제안한다. 피부색을 통한 얼굴 후보를 추출하고 그 외의 배경 이미지는 삭제하여 연산처리를 빠르게 하였다. Viola-Jones가 제안한 얼굴검출 알고리즘을 POSIX Thread를 사용하여 병렬 처리하였고 그 성능을 단일 코어와 멀티코어에서 측정하였다. 단일 코어에서는 성능의 향상이 없었으나 멀티코어에서는 약 1.8배 속도가 향상되었고 검출 성공률은 기존과 동일하였다.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.140-142
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• 2008

Thrust ripples in Permanent Magnet Linear Motor(PMLSM) are mainly generated by cogging force. Cogging force caused by the interaction between the iron core and the Permanent Magnet(PM), and end effect. This paper has proposed a control method for thrust ripples suppression and design of one-chip proceeding digital controller using TMS320LF2407. This control method is realized by Field Oriented Control(FOC) adding to current compensation. The effectiveness of proposed control method is verified by experimentation comparing between the compensation and non-compensation.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.711-713
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• 2004

In the past time, the protection relay did only a protection function. Currently, its upgraded device i.e. IED(Intelligent Electric Device) has been designed to protect, control, and monitor the whole power system automatically. Also the device is desired to successfully measure important elements of the power system. This paper considers design method of a digital protection IED with a function of measuring various elements and a communication function. The protection IED is composed of the specific function modules that are signal process module, communication module, input/output module and main control module. A signal process module use a DSP processor for analysis of input signal. Main control module use a embedded processor, Xscale, that has an ARM Core. The communication protocol uses IEC61850 protocol that becomes standard in the future. The protection IED is able to process mass information with high-performance processor. As each function module is designed individually, the reliability of the device can be enhanced.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.19-22
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• 2000

최근 이동전화의 사용이 급격히 확산됨에 따라 핸즈프리 단말기를 이용한 전화통신의 필요성이 대두되고 있다. 차량내 핸즈프리 통신상황의 경우 근거리에 위치한 스피커와 마이크로폰의 커플링에 의해 발생하는 음향반향과 차량내에 존재하는 배경잡음은 통화 품질을 크게 저하시킨다. 본 논문에서는 이동통신에 적합한 음향반향제거기와 잡음제거기의 결합시스템을 제안하고, 이를 고정 소수점 DSP를 이용하여 실시간 구현하였다. 실시간 구현을 위하여 음향반향제거기에는 NLMS 알고리즘에 의해 구동되는 제한된 차수의 적응반향제거기법을 사용하였다. 잔여반향 및 배경잡음제거를 위해 CDMA방식의 셀룰라 이동통신에 사용되는IS-127 EVRC음성 부호화기의 표준안에 포함된 잡음제거방식을 사용하였다. 제안된 시스템을 16 비트 고정소수점DSP인 OAK DSP Core를 이용하여 약 18.6MIPS의 연산량으로 실시간 구현되었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.