• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.397-399
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• 1995

An UPS must be synchronized in frequency and phase relationship with the mains power supply. This paper describes and tests a digital phase-locked loop(DPLL) circuit of the open-loop method designed by full software with TMS320c31 digital signal processor. finally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.87-88
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• 2011

본 논문은 최근 빠른 속도로 성장하고 있는 신재생에너지 분야 중 태양광을 이용한 계통연계형 PV PCS의 PLL(Phase Locked Loop) 기법을 DSP로 처리할 수 있도록 디지털 논리회로로 구현하는 DPLL(Digital Phase Locked Loop) 기법을 제시하고 모델링과 시뮬레이션을 통하여 검증한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.4
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• pp.591-598
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• 2021

The digital phase-locked loops(DPLL) is a circuit used for phase synchronization and has been generally used in various fields such as communication and circuit fields. State estimators are used to design digital phase-locked loops, and infinite impulse response state estimators such as the well-known Kalman filter have been used. In general, the performance of the infinite impulse response state estimator-based digital phase-locked loop is excellent, but a sudden performance degradation may occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a minimum variance finite impulse response filter with optimal horizon for designing a new digital phase-locked loop. A numerical method is introduced to obtain the measured value interval length, which is an important parameter of the proposed finite impulse response filter, and to obtain a gain, the covariance matrix of the error is set as a cost function, and a linear matrix inequality is used to minimize it. In order to verify the superiority and robustness of the proposed digital phase-locked loop, a simulation was performed for comparison and analysis with the existing method in a situation where noise information was inaccurate.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.6-12
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• 1984

The basic binary quantized first-order digital phase locked loop (DPLL) is modified in order to reduce the aquisition time and steadyftate phase error. Adding the loop that corrects the phase difference by detecting the falling zero-crossing time, an effort for the improving the performance is performed and the performance compared with that of the basic DPLL. Using a graphical method, the phase locking processes of the modified DPLL for a phase step and a frequency step input are depicted visually in the absence of noise. The performance of the modified DPLL for a sinusoidal input added narrow band random noise is evaluated using the Chapman-Kolmogorov equation. This approach is verified by direct computer simulation. The steady-state phase error and the average aquisition time of the modified DPLL are compared with those of the basic DPLL, It is shown that the aquisition time of the modified DPLL is shortened about twice, also, as signal to noise ratio increases, the effect of the modification increases and the steady-state phase error approaches to zero.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.55-67
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• 1982

In this Paper new results relating to the acquisition behavior of a class of first-and secondorder digital phase-locked loops (DPLL) originally proposed by Reddy and Cupta are presented in the absence of noise. It has been found that the number of quantization levels L and the number of phase error states N play important roles in acquisition. For a given L-level quantizer, as N increases, the acquisition time increases, and the lock range decreases. However, the deviation of the steady state phase error decreases in this case. When L increases, the acquisition time decreases, and the lock range increases. However, variation of L affects little for the steady state phase error. In addition, the effects of a loop filter on acquisition have also been considered. One can get smaller acquisition time and larger lock range as the filter parameter value becomes larger. However, deviation of the steady state phase error increases in that case. Analytical results have been verified by computer simulation.

• Journal of Astronomy and Space Sciences
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• v.27 no.2
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• pp.145-152
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• 2010

In this paper, we developed a local oscillator (LO) system of millimeter wave band receiver for radio astronomy observation. We measured the phase and amplitude drift stability of this LO system. The voltage control oscillator (VCO) of this LO system use the 3 mm band Gunn oscillator. We developed the digital phase locked loop (DPLL) module for the LO PLL function that can be computer-controlled. To verify the performance, we measured the output frequency/power and the phase/amplitude drift stability of the developed module and the commercial PLL module, respectively. We show the good performance of the LO system based on the developed PLL module from the measured data analysis. The test results and discussion will be useful tutorial reference to design the LO system for very long baseline interferometry (VLBI) receiver and single dish radio astronomy receiver at the 3 mm frequency band.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.250-254
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• 2007

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive powers of the load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• Journal of the Korean Solar Energy Society
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• v.27 no.2
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• pp.37-44
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• 2007

As photovoltaic(PV) power generation system becomes more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of the load and PV system are closely matched, islanding detection by Passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2180-2183
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• 2003

본 논문에서는 광 디스크의 기록 밀도 증가에 따른 신호품질의 열화나 노이즈가 심한 환경에서 DPLL(Digital Phase Locked Loop)의 성능을 개선하기 위한 FD(Frequency Detector)와 PD(Phase Detector) 알고리즘을 제안한다. 제안된 PD 알고리즘은 노이즈에 의해 왜곡되어 RLL 조건을 위배하는 입력신호, 즉 RLL 조건에 의해 결정되는 최소 런 길이보다 주기가 작은 신호에 의해 발생하는 위상오차를 위상오차 보정 시 사용하지 않도록 설계하여 잘못된 정보에 의한 위상오차 보정이 일어나지 않도록 하였다 제안된 FD 알고리즘은 주파수를 추적하기 위해 삽입되는 신호인 Sync 신호의 symmetry 특성을 이용하여 샘플패턴을 검출하도록 하여 기존의 주파수 오차 보정 알고리즘보다 향상된 주파수 추적 성능을 가지도록 하였다.