• Journal of Digital Contents Society
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• v.10 no.2
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• pp.217-223
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• 2009

In order to decrease the power consumption in Embedded Linux environment based on XScale PXA255, We produce the device driver of DFS(Dynamic Frequency Scaling) technique, design and implement the middleware DFM(Dynamic Frequency Management) to scale the power of embedded target board with porting this device drive, suggest the method to reduce the Embedded system's power consumption.

• ETRI Journal
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• v.44 no.5
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.464-469
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• 2007

현재 이동용 장치(Mobile Device)들에서 전력 소모는 사용자들의 요구에 따라 성능 다음으로 중요한 비중을 차지하고 있다. 특히 배터리 셀의 기술 증가에 비해 프로세서들의 성능 및 요구하는 소비전력이 크게 증가함에 따라 프로세서의 전력 소모를 최소화 하는 연구들이 많이 진행되고 있다. 특히 프로세서의 전력 소모가 많은 비중을 차지함에 따라 프로세서의 전력 소모를 낮추기 위한 방법으로 많은 프로세서들은 DVS(Dynamic Voltage Scaling)와 DFS(Dynamic Frequency Scaling)를 지원한다. 실제 프로세서의 전력 소모는 공급전압에 의 제곱에 비례하고 동작 클럭(Clock) 주파수에 비례한다. 그러나 공급전압은 다시 동작 클럭 주파수에 비례함으로써 DVS와 DFS를 지원하는 대부분의 프로세서는 동작 클럭 주파수를 낮춤으로서 많은 전력 소모를 줄일 수 있게 된다. 그러나 동작 클럭 주파수를 낮추게 되면 태스크들의 실행 시간이 길어지게 되어 실시간 시스템에서 실시간성을 보장하지 못하게 된다. 본 논문에서는 상호간에 공유자원을 갖는 태스크들의 실시간성을 보장하며 동작 클럭 주파수를 낮추는 알고리즘을 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.26 no.8
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• pp.1-11
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• 2021

This paper proposes a novel mechanism called Event-driven Uncore Frequency Scaler (eUFS) to improve the energy efficiency of the HPC systems. UFS exploits the hardware events such as LAPI (Last-level Cache Accesses Per Instructions) and CPI (Clock Cycles Per Instruction) to dynamically adjusts the uncore frequency. Hardware events are collected at a reference time period, and the target uncore frequency is determined using the collected event and the previous uncore frequency. Experiments with the NPB benchmarks demonstrate that the eUFS reduces the energy consumption by 6% on average for class C and D NPB benchmarks while it only increases the execution time by 2% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.