• 대한전자공학회논문지SD
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• 제46권12호
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• pp.1-9
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• 2009

가산기는 기본적인 산술 연간 장치로써, 산술 연산 시스템 전체의 속도 및 전력소모에 결정적인 역할을 한다. 단일 비트 전가산기의 성능을 향상시키는 문제는 시스템 성능 향상의 기본적인 요소이다. 주 논문에서는 기존의 모듈 I과 모듈III를 거쳐 출력 Cout을 갖는 XOR-XNOR 구조와는 달리 모듈 I을 거치지 않고 입력 A, B, Cin에 의해 모듈III를 거쳐 출력 Cout을 갖는 새로운 구조를 이용한다. 최대 5단계의 지연단계를 2단계로 줄인 전가산기를 제안한다. 따라서 Cout 출력속도가 향상되어 리플캐리 가산기와 같은 직렬연결의 경우 더욱 좋은 성능을 나타내고 있다. 제안한 1Bit 전가산기는 static CMOS, CPL, TFA, HPSC, TSAC 전가산기에 비해 좋은 성능을 가지고 있다. 가장 좋은 성능을 나타내는 기존의 전가산기에 비해 4.3% 향상된 지연시간을 가지며 9.8%의 향상된 PDP 비율을 갖는다. 제안한 전가산기 회로는 HSPICE 툴을 이용하여 $0.18{\mu}m$ CMOS 공정에서 전력소모 및 동작속도를 측정하였으며 공급전압에 따른 특성을 비교하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.965-969
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• 2008

MgO thin film is widely used in PDP panel for protecting the dielectric layer and making firing voltage low. In this paper, the MgO thin film and discharge characteristics was analyzed as hydrogen flow rate increasing. Using hydrogen in deposition chamber makes add delay time of PDP module longer or shorter. It is the reason why thin film surface layer thickness on the MgO surface changes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.505-507
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• 2005

In this paper, a timing analysis is performed for the CAN-based simulator system for a fuel cell hybrid electric vehicles. The CAN protocol is recently being used for conventional vehicles, however, the network-induced delay can make the in-vehicle network system unstable. This problem may be occurred in the future vehicles because more ECUs are being required than recent vehicles. In order to develop a stable network-based control system, timing analysis is required at the design process. Throughout this analysis, timing parameters that affect transmission delay are examined and an effective method of predicting a sampling time for a stable communication via CAN protocol. In order to show the validityof suggested timing analysis. some experiments are performed using DSPs with CAN module.

• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• 한국통신학회논문지
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• 제21권8호
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• pp.2033-2042
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• 1996

In this papre, we describe a recently implemented echo canceller for digital cellular communication of Code Division Multiple Access(CDMA) that features time sharing of digital signal processor(DSP) over four channels in one DSP to reduce per channel costs. In the Public Land Mobile Network(PLMN), it is important to cancel the echo reflected from the Public Switched Telephone Network(PSTN) side. In case of digital mobile system, the round-trip delay of the echo is in excess of about 180 milliseconds due to frame-by-frame voice coding. It is necessary to cancel the echo in PLMN. We have developed a multi-channel echo canceller tht operates with Time Switch Module in a Mobile Switching Center(MSC). The general echo canceller needs PCM trunk interface circuits and the tone detection and disabling circuits, but the multi-channel echo canceller linked with Time Switch Module does not need them. Therefore we could develop the effective and economical echo canceller.

• 전자공학회논문지A
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• 제30A권12호
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• pp.117-124
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• 1993

In this paper we propose a new thchnology mapping algorithm for multiplexer-based FPGA's The algorithm consists of three phases` First, it converts the logic functions and the basic logic mocule into BDD's. Second. it covers the logic function with the basic logic modules. Lastly, it reduces the number of basic logic modules used to implement the logic function after going through cell merging procedure. The binate selection is employed to determine the order of input variables of the logic function to constructs the balanced BDD with low level. That enables us to constructs the circuit that has small size and delay time. Technology mapping algorithm of previous work used one basic logic module to implement a two-input or three-input function in logic functions. The algorithm proposed here merges almost all pairs of two-input and three-input functions that occupy one basic logic module. and improves the mapping results. We show the effectiveness of the algorithm by comparing the results of our experiments with those of previous systems.

• Journal of Electrical Engineering and Technology
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• 제7권3호
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• pp.366-375
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• 2012

This paper describes a design and temporal analysis of a hardware-in-the-loop (HIL) simulation environment for testing a motor control unit (MCU). The design concepts and main characteristics including unavoidable time delays of each component module are described. From temporal analysis results according to the module integration method, an appropriate solution is proposed to fix and minimize time delays. In order to verify the effectiveness of the proposed solution, the HIL test results are compared with the results of experiments and an offline simulation.

• 한국전자파학회논문지
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• 제29권2호
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• pp.99-108
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• 2018

본 논문은 마그네트론 대체를 위한 반도체 전력 발진기 모듈 설계에 관련된 내용을 기술하였다. 300급 LDMOS 단일 전력 증폭기의 특성을 확인하였고 두 개를 결합하여 모듈을 구성하였다. 결합된 모듈에 delay-line feedback loop을 구성하고 위상 천이기를 이용하여 위상을 조절하여 발진기를 구동시켰다. 발진기 모듈 측정 결과 주파수 2.327 GHz에서 출력 800 W, 효율 58 %로 측정되었다. 이 결과는 시뮬레이션 결과와 유사한 특성을 보여준다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 춘계종합학술대회
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• pp.395-398
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• 2004

본 논문은 원격지의 데이터와 각종 디바이스들을 ON/OFF 하고, 상태를 웹 브라우져를 통하여 실시간으로 확인 할 수 있도록 하는 임베디드 시스템과 응용모듈 제작에 관한 논문이다. 최근 초고속 인터넷 발달과 인터넷 시설이 잘 갖추어진 특성 때문에 원격지의 각종 데이터와 디바이스 상태들을 직접 실시간으로 제어하고 검출할 수 있는 기술은 다방면으로 응용분야가 광범위하다고 생각된다.

• ETRI Journal
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• 제44권6호
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• pp.1020-1033
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• 2022

In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.