• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.171-181
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• 1988

In this study, a packet voice/data terminal(PVDT) that services both voice and data in the packet-switched network is implemented. The software structure of the PVDT is designed according to the OSI 7 layer architecture. The discrimination of voice and data is made in the link layer. Voice packets have priority over data packets in order to minimize the transmission delay, and are serviced by a simple protocol so that the overhead arising form the retransmission of packets may be minimized. The hardware structure of the PVDT is divided into five modules; a master control module, a speech proessing module, a speech activity detection module, a telephone interface module, and an input/output interface module. In addition to the hardware implementation, the optimal reconstruction delay of voice packets to reduce the influence of delay variance is analyzed.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.4
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• pp.603-610
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• 2004

Time delays are included in most of actual systems, and some of which are shown as time varying. To analyze the time varying time delay system in the time domain. a useful delay module to express the function as a tool is much helpful to get corresponding outputs under given conditions. A method is proposed here to design the algorithm of time delay module for simulation or control purposes, including the problems of initializing and reallocating data in buffer. After classifying the time varying time delay into the distributed mode and lumped mode, an object to describe delay module is configured and tested under the defined input signal and given time delay variation. The simulation results show that the output of module matches reasonably with the case of real system.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.6
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• pp.401-408
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• 2019

The objective of this study is to develop a new type of buried sensor module that can directly assess pre-stressed concrete by measuring strain using a hetero-core optical fiber sensor. In this regard, experiments were conducted to evaluate the performance of the sensor using an exposure sensor module. Based on the experimental results, when the values of the displacement control velocity were 0.12 mm/min and 1.80 mm/min, the corresponding delays in the measurement were 52.1 s and 2.6 s respectively, which indicated that the maximum delay between the two measurements was a factor of 19. Due to the measurement delay phenomena, the sensor module used in the experiments cannot be employed to check the real-time state of the structure. Thus, additional experiments were needed to develop a new sensor module that can measure the real-time state of the structure. To investigate the cause of the measurement delay phenomena, three experiments were conducted. It was confirmed that measurement delay is mainly attributed to frictional resistance. The measurement delay phenomena were not observed in the experiments using the friction-removed device.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.1
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• pp.7-13
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• 2005

In this paper, we propose the time synchronization module on fiber optic repeater to use optic line delay for obtaining time synchronization between up-link and down-link, in the 2.3 GHz WiBro network using TDD/OFDM (Time Division Duplex/Orthogonal Frequency Division Multiplexing) Generally, when we use fiber optic repeater to remove the shade area, it occurs transmission delay which is caused by optic transmission between RAS (Radio Access Station) and fiber optic repeater and inner delay of fiber optic repeater. Because the WiBro system is adopting a TOO method and there exists the difference of switching time which is caused by these delay between up-link and down-link, it occurs ISI (Inter Symbol Interference), ICI (Inter Carrier Interference). These interference results in the reduction of the coverage. And the inconsistency between Up-Link and Down-Link switching time maybe gives rise to the interruption of communication. In order to prevent these cases, we propose synchronization module using analog optic line delay as the one of synchronizing up-link and down-link. And we propose the consideration factor for the designing time synchronization module and the feature of optic line of analog method. The measurement result of optic line time synchronization module of structure proposed is as follows, the delay error of $0.5{\mu}g$ and the insertion loss value below maximum 4.5dB in range of $0{\sim}40{\mu}s$. These results fully meet the specification of WiBro System.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.243-246
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• 2001

A cavity delay filter module for IMT-2000 LPA has been developed with 0.9dB insertion loss, 0.1dB/0.6$^{\circ}$ gain/phase flatness. Broadband signal cancellation of the module has been simulated using the measured S parameter, and gain, phase and group delay have been matched to satisfy the signal cancellation of the module. In the experiment, the value of designed parameters are used and 40dB signal cancellation has been obtained over 100MHz bandwidth. Also the sampling cancellation has been shown to be the similar performance of the feedforward output cancellation.

• Journal of Korea Multimedia Society
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• v.20 no.11
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• pp.1803-1810
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• 2017

A large amount of processing time is required if the process of detecting the touch position on the touch screen and displaying it on the display panel is performed only by software. In this paper, we propose a method to output information touched on the screen using H/W method in order to improve the response speed delay. In the FPGA module designed for the HDMI signal output to the display module, the touch information is input to the serial data signal including touch coordinate information, point size, and color information. Then the module render the image using HDMI signal input to the module and the touch information. This method has a pipeline structure so it has effect of reducing the delay time that occurs in outputting the touch information compared with the conventional software processing method.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.459-462
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• 2004

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.4
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• pp.220-232
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• 2012

In this paper, we investigate the correlation result due to the problems of delay tracking and fringe rotation module in the VCS(VLBI Correlation Subsystem). The VCS, FX-type correlator, adopts the delay tracking and fringe rotation module in order to compensate the delay change and fringe phase of wave signal from the radio source by Doppler's effect. The phase of observed data is also compensated by means of delay tracking and fringe rotation in the correlator, but we confirmed that the phase is unstable by applying long integration period of AIPS(Astronomical Image Processing System) rather than correlator. And the delay value of observed data has the errors of several tens nanoseconds than normal case at the analysis of correlation result. In addition, we found that the phase of correlation results is not connected as the unit of FFT-segment because the initial fringe phase at the fringe rotation module is not correctly determined. In this paper, in order to solve these problems, the original direction of 90 degree phase jump is reversely modified when the bit-shift occurred at the delay tracking. And the initial fringe phase at the fringe rotation module is correctly modified by using the initial phase of observed data. In addition, the parameter calculation module was abnormally operated as designed in the fringe rotation. So, the logical program by the VCS is modified so as to calculate the parameters correctly. Through the experiments of correlation processing over the above problems, the modified proposal algorithm is adequately corrected to the data analysis results, so that the experimental results make it clear for us to operate the developed VCS hardware correlator normally.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.741-748
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• 2005

Power saving module which is consisted of ferroelectric ceramic capacitor and time delay switching circuit was installed into electronic ballast in order to enhance energy efficacy and extend life time of fluorescent lamp. The impedance matching of negative resistance characteristics of F/L was optimized with the characteristics of ferroelectric ceramics capacitor to increase the light efficiency of the electronic ballast. The high efficiency of the electronic ballast was achieved by minimizing wasted power at the filament of F/L during the lighting by using the switching function of time delay circuit from preheating mode to non-preheating mode. The life time of F/L was also extended by eliminating the reverse electromotive force using time delay circuits to minimize the impacts to the filament of F/L from unwanted high voltage peaks during light-up period. As the results, the electronic ballast with the first grade energy efficiency was developed using ferroelectric ceramics and time delay module.