• International Journal of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.74-83
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• 2023

In this paper, we propose an image compression scheme which uses a demosaicking network and a channel-wise decoder in the decoding network. For the demosaicing network, we use as the input a colored mosaiced pattern rather than the well-known Bayer pattern. The use of a colored mosaiced pattern results in the mosaiced image containing a greater amount of information pertaining to the original image. Therefore, it contributes to result in a better color reconstruction. The channel-wise decoder is composed of multiple decoders where each decoder is responsible for each channel in the color image, i.e., the R, G, and B channels. The encoder and decoder are both implemented by wavelet based auto-encoders for better performance. Experimental results verify that the separated channel-wise decoders and the colored mosaic pattern produce a better reconstructed color image than a single decoder. When combining the colored CFA with the multi-decoder, the PSNR metric exhibits an increase of over 2dB for three-times compression and approximately 0.6dB for twelve-times compression compared to the Bayer CFA with a single decoder. Therefore, the compression rate is also increased with the proposed method than with the method using a single decoder on the Bayer patterned mosaic image.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.1-11
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• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.659-660
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• 2006

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.361-370
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• 1997

In this paper, we designed POCSAG Signal Decoder to improve operating time in pager. We showed POCSAG Signal Pattern sent by transmitter and operation of this decoder. We also showed that the Pager using this decoder was equipped with Wide Area Signal Detection and designed the hardware which realizes this operation and implemented it with ASIC chip. As we inspected the function of the ASIC chip and tested the performance, we could find that the chip operated in low voltage and that power dissipation was low.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.240-246
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• 2008

An MPEG-2/4 AAC decoder on 16-bit fixed-point processor is presented in this paper. To meet audio quality criteria, despite small word length, special design methods for 16-bit foxed-point AAC decoder were devised. This paper presents particular algorithms for 16-bit AAC decoding. We have implemented an efficient AAC decoder using the proposed algorithms. Audio contents can be replayed in the decoder without quality degradation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.285-288
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• 2000

In this paper, we propose a Reed-Solomon decoder for the DVD Reed-Solomon(RS) product code based on new efficient euclid cell architecture suitable for Modified Euclid Algorithm. We synthesized the RS decoder using Hyundai 0.65um CMOS standard cell library and compared the performance of the decoder with one of the conventional architectures. The result shows that the proposed euclid cell use about 32% less symbol time.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.863-866
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• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.