• 전력전자학회논문지
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• 제18권2호
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• pp.145-152
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• 2013

Electrolytic capacitors used for smoothing DC link voltage is one of the major root causes of fault in power electronic system. The aging of aluminum electrolytic capacitors is expressed by the increase of their equivalent series resistance (ESR) and the reduction of their capacitance. Thus, the proposed technique in this paper is to measure capacitance, by comparing energy loss of DC link capacitors with stator resistor in electric machine. Condition of DC link capacitors can be estimated from the capacitance decrease rate between initial and aged capacitors. The results show that the proposed technique provides an easy, widely applicable and simple low cost solution for detecting dc link capacitor degradation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.370-371
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• 2011

This paper presents a control algorithm that minimizes the DC-link capacitance by decreasing the capacitor current. The capacitor current can be nullified by a feedback compensation term which is calculated from the power balance in the AC/DC converter. As a result, voltage variation in the DC-link is reduced further, which makes a large reduction in the size of DC-link capacitors which are expensive and have limitations in life time. Simulations are performed with two 80uF DC-link capacitors, which can be replaced by film capacitors.

• 전력전자학회논문지
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• 제27권4호
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• pp.291-296
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• 2022

Capacitor is one of the reliability-critical components in power converters. The lifetime of the capacitor decreases as the operating temperature increases, and power losses caused by capacitor current are the main cause of the capacitor temperature increase. Therefore, various studies are being conducted to improve the lifetime of the capacitor by reducing the current of DC-link capacitors. In this study, pulse width modulation methods proposed for improving the lifetime of DC-link capacitors of the three-level NPC inverter are comparatively analyzed. The lifetime evaluation of the DC-link capacitor under different modulation methods is performed at component level first and then system level by considering all capacitors by applying Monte Carlo simulation. Furthermore, their effects on the efficiency and THD of the output current are also considered.

• 전력전자학회논문지
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• 제26권2호
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• pp.120-126
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• 2021

DC-link capacitors are one of the main components in two-level three-phase voltage source inverters (VSIs); they provide the pulsating input current and stabilize the vacillating DC-link voltage. Ideally, the larger the capacitance of DC-link capacitors, the better the DC-link voltage stabilizes. However, high capacitance increases the cost and decreases the power density of VSI systems. Therefore, the capacitance should be chosen carefully on the basis of the DC-link voltage ripple requirement. However, the DC-link voltage ripple is dependent on the pulse-width modulation (PWM) strategy. This study especially presents a DC-link voltage ripple analysis when the minimum loss discontinuous PWM strategy is applied. Furthermore, an equation for the selection of the minimum capacitance of DC-link capacitors is proposed. Experimental results with R-L loads are also provided to verify the effectiveness of the presented analysis.

• Journal of Power Electronics
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• 제18권1호
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• pp.116-128
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• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• 전기학회논문지P
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• 제58권4호
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• pp.391-396
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• 2009

In this paper, a control algorithm for DC-Link voltage unbalancing compensation of a four-switch inverter for a three-phase BLDC motor drive is proposed. Compared with a conventional six-switch inverter, the split source of the four-switch inverter can be obtained by splitting DC-link capacitor into two capacitors to drive the three phase BLDC motor. The voltages across each of two capacitors are not always equal in steady state because of the unbalance in the impedance of the DC-link capacitors $C_1$ and $C_2$ or the variable current flowed into the capacitor's neutral point in motor control. Despite the unbalance, if the BLDC motor may be run for a long time the voltage across one of the capacitors is more increased. So the unbalance in the capacitors voltages will be accelerated. As a result, The current ripple and torque ripple is increased due to the fluctuation of input current which flows into 3-phase BLDC motor. According to that, the vibration of motor will be increased and the whole system will be instable. This paper presents a control algorithm for DC-Link voltage unbalancing compensation. The sampling from the voltages across each of two capacitors is used to perform the voltage control of DC-Link by using the feedforward controller.

• 조명전기설비학회논문지
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• 제27권7호
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• pp.59-66
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• 2013

This paper proposes a new voltage reference generation method for Four-Switch Inverters(FSI) with compensation of the neutral DC-link voltage variation. Since FSIs have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, it is required to take account the voltage difference between the top and bottom capacitors. In this paper, to reduce the effect by the voltage variation, reference voltages are modified by adding compensation voltages proportional to the voltage difference between upper and lower capacitors. Simulation results showing control performance of induction and permanent magnet motors demonstrate the validity of the proposed method.

• Journal of Power Electronics
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• 제19권5호
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• pp.1133-1141
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• 2019

In this paper, a capacitors energy strategy based Cascaded H-bridge Converter (CHBC) for steady DC link voltage is proposed, which allow the CHBC to work while DC power fails. The topology of the CHBC is analyzed to construct the proposed strategy. The capacitors energy strategy is deduced based on the principle that the DC link voltage should be steady, the switch state should be smooth and the switch frequency should be normal. Experiments based on a three-module prototype, including static experiment, start experiment and step change experiment, proves the correctness of the strategy. They also verified the excellent fault tolerance ability and good dynamic performance of the proposed strategy.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.277-279
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• 2008

In this paper, a novel active boost converter for SR drive is proposed. An active capacitor circuit is added in the front-end. Based on this active capacitor network, when boost switch turns off, this network seems as passive capacitor network. And the voltage of boost capacitor can keep balance with dc-link voltage automatically. In the capacitor network, discharging voltage is general dc-link voltage in parallel-connected capacitors; charging voltage is double dc-link voltage in series-connected capacitors. When boost switch turns on, two capacitors are connected in series, and discharging voltage is up to double dc-link voltage. So the fast excitation current can be obtained from this mode. Profit from fast excitation and fast demagnetization mode, the performance and output power can be improved. Some computer simulations are done to verify the performance of proposed converter.

• 전력전자학회논문지
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• 제27권6호
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• pp.535-540
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• 2022

DC-link capacitors are reliability-critical components in a photovoltaic (PV) inverter. Typically, the lifetime of a DC-link capacitor is evaluated by considering the voltage and hot-spot temperature of the capacitor under the specific operating condition of the PV inverter. However, the output of the PV inverter is determined by solar irradiation and ambient temperature, which vary with the seasons; accordingly, the hot-spot temperature of the capacitor also changes. Therefore, the mission profile of the PV system should be considered to effectively evaluate the reliability of the DC-link capacitor. In this study, the reliability of the DC-link capacitor of a three-level NPC inverter is comparatively analyzed with and without considering the mission profiles of the PV system, where two mission profiles recorded in Arizona and Iza are considered. The accumulated damage of the DC-link capacitor is calculated based on the lifetime model by analyzing its thermal loading. Afterward, a reliability evaluation of the DC-link capacitor is performed at the component level and then at the system level by considering all capacitors by means of Monte Carlo analysis. Results reveal the importance of performing a mission-profile-based reliability evaluation during the design of high-reliability PV inverters to achieve the target reliability performance.