• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.8-13
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• 2001

Cerium oxide ($CeO_2$) thin film has been proposed as a buffer layer between the ferroelectric thin film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS) structures for ferroelectric random access memory (FRAM) applications. In this study, $CeO_2$ thin films were etched with $Cl_2$/Ar gas mixture in an inductively coupled plasma (ICP). Etch properties were measured for different gas mixing ratio of $Cl_2$($Cl_2$+Ar) while the other process conditions were fixed at RF power (600 W), dc bias voltage (-200 V), and chamber pressure (15 mTorr). The highest etch rate of $CeO_2$ thin film was 230 ${\AA}$/min and the selectivity of $CeO_2$ to $YMnO_3$ was 1.83 at $Cl_2$($Cl_2$+Ar gas mixing ratio of 0.2. The surface reaction of the etched $CeO_2$ thin films was investigated using x-ray photoelectron spectroscopy (XPS) analysis. There is a Ce-Cl bonding by chemical reaction between Ce and Cl. The results of secondary ion mass spectrometer (SIMS) analysis were compared with the results of XPS analysis and the Ce-Cl bonding was monitored at 176.15 (a.m.u). These results confirm that Ce atoms of $CeO_2$ thin films react with chlorine and a compound such as CeCl remains on the surface of etched $CeO_2$ thin films. These products can be removed by Ar ion bombardment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1167-1172
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• 2013

This paper presents a X-band doppler radar with high conversion gain using a self-oscillating-mixer(SOM) that oscillation and frequency mixing is realized at the same time. To improve phase noise of the SOM oscillator, a ${\lambda}/2$ slotted square patch resonator(SSPR) was proposed, which shows high Q-factor of 175.4 and the 50 % reduced circuit area compared to the conventional resonator. To implement the low power system, low biasing voltage of 1.7 V was supplied. To enhance the conversion gain of the SOM, bias circuit is configured near the pinch-off region of transistor, and the conversion gain was optimized. The output power of the proposed SOM was -3.16 dBm at 10.65 GHz. A high conversion gain of 9.48 dB was obtained whereas DC Power consumption is relatively low about 7.65 mW. The phase noise is -90.91 dBc/Hz at 100 kHz offset. The figure-of-merit(FOM) of the proposed SOM was measured as -181.8 dBc/Hz, which is supplier to other SOMs by more than about 7 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.492-501
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• 2013

In this paper, a multi polarization reconfigurable microstrip antenna that can be used selectively for four polarizations(vertical polarization, horizontal polarization, right hand circular polarization, left hand circular polarization) at the S-band is presented. The proposed antenna consists of four PIN diodes and a microstrip patch with a cross slot and a circular slot and is fed by utiliting electromagnetic coupling between the microstrip patch and the feed line. The proposed antenna has a DC bias network to supply DC voltage to each PIN diode and the polarization can be determined by controlling the ON /OFF states of four PIN diodes. The fabricated antenna has a VSWR below 2 in the vertical polarization(3.17~3.21 GHz), the horizontal polarization(3.16~3.20 GHz), the left hand circular polarization (3.08~3.19 GHz), and the right hand circular polarization(3.10~3.2 GHz) frequency bands. The designed antenna has the cross polarization level higher than 20 dB, a gain over 5 dBi for the linear polarization states, and 3 dB axial ratio bandwidth wider than 50 MHz in the circular polarization states.

• Journal of Astronomy and Space Sciences
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• v.20 no.4
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• pp.339-350
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• 2003

Engineering qualification model payload for a communications and broadcasting satellite(CBS) was developed by ETRI from May, 2000 to April, 2003. For. the purpose of functional test and verification of the payload, a real-time hardware-in-the-loop(HITL) CBS simulator(CBSSIM) was also developed. We assumed that the spacecraft platform for the CBSSIM is a geostationary communication satellite using momentum bias three-axis stabilization control technique based on Koreasat. The payload hardware is combined with CBSSIM via Power, Command and Telemetry System(PCTS) of Electrical Ground Support Equipment(EGSE). CBSSIM is connected with PCTS by TCP/IP and the payload is combined with PCTS by MIL-STD-1553B protocol and DC harness. This simulator runs under the PC-based simulation environment with Windows 2000 operating system. The satellite commands from the operators are transferred to the payload or bus subsystem models through the real-time process block in the simulator. Design requirements of the CBSSIM are to operate in real-time and generate telemetry. CBSSIM provides various graphic monitoring interfaces and control functions and supports both pre-launch and after-launch of a communication satellite system. In this paper, the HITL simulator system including CBSSIM, communications payload and PCTS as the medium of interface between CBSSIM and communications payload will be described in aspects of the system architecture, spacecraft models, and simulator operation environment.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.619-628
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• 2019

In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

• Journal of Navigation and Port Research
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• v.28 no.5
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• pp.429-434
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• 2004

In this paper, we designed a reconfigurable slot antenna using sequentially voltage-applied RF MEMS switches. In order to obtain pull-in voltage and maximum stress of the MEMS switches, the switch structures in accordance with airgap height was analyzed by ANSYS simulation A actuation voltage of MEMS switches can be determined by switch geometry and airgap height between a movable plate and a bottom plate. The designed lengths of MEMS switches were 240 $\mu\textrm{m}$, 320 $\mu\textrm{m}$, 400 $\mu\textrm{m}$, respectively and the airgap was 6$\mu\textrm{m}$. The total size of the designed slot antenna was 10 mm x 10 mm and the slot length and width were 500 $\mu\textrm{m}$ and 200 $\mu\textrm{m}$, respectively. The length and size of the CPW feedline were 5 mm and 30-80-30 $\mu\textrm{m}$, respectively. and then the size of the CPW in the slot was 50-300-150 $\mu\textrm{m}$. The tuning of the resonant frequency of the proposed device is realized by varying the electrical length of the antenna, which is controlled by applying the DC bias voltages to the RF MEMS switches. The designed slot antenna has been simulated, fabricated and measured.

• Journal of the Korean Magnetics Society
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• v.27 no.4
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• pp.115-122
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• 2017

The antiferromagnet IrMn based four different GMR-SV multilayers on Corning glass were prepared by using ion beam deposition and DC magnetron sputtering system. The magnetoresistance (MR) properties for single-type and dual-type GMR-SV multilayer films were investigated through the measured major and minor MR curves. The exchange bias coupling field ($H_{ex}$) and coercivity ($H_c$) of pinned layer, the $H_c$ and interlayer exchange coupling field ($H_{int}$) of free layer for the dual-type structure GMR-SV multilayer films consisted of top IrMn layer were 410 Oe, 60 Oe, 1.6 Oe, and 7.0 Oe, respectively. The minor MR curve of two free layers was performed the squarelike feature having a MR ratio of 8.7 % as the sum of 3.7 % and 5.0 %. The value of average magnetic field sensitivity (MS) was maintained at 2.0 %/Oe. Also, the magnetoresistance properties of the single-type and dual-type structure GMR-SV multilayer films consisted of bottom IrMn layer were decreased more than those of top IrMn layer. Two antiparallel states of magnetization spin arrays of the pinned and free layers in the dual-type GMR-SV multilayer films occurred the maximum MR value by the effect of spin dependence scattering.