• Title/Summary/Keyword: DC-bias

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Design and Measurement of an SFQ OR gate composed of a D Flip-Flop and a Confluence Buffer (D Flip-Flop과 Confluence Buffer로 구성된 단자속 양자 OR gate의 설계와 측정)

  • 정구락;박종혁;임해용;장영록;강준희;한택상
    • Progress in Superconductivity
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    • v.4 no.2
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    • pp.127-131
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    • 2003
  • We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

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Linearity of All Optical Dual EA Modulator for Narrow-band Microwave Optical Transmissions (협대역 마이크로파 광전송을 위한 전광 이중 전계흡수 광변조기의 선형특성)

  • Lee, Gyu-Woong;Han, Sang-Kook
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.6
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    • pp.87-96
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    • 1999
  • For analog optical transmission of narrow-band microwave signal, a novel all-optical linearization technique of electro-absorption (EA) optical modulator by using dual modulation scheme is proposed and theoretically investigated. By using the dual modulation scheme where the sub-modulator has a different length, DC bias and band-gap wavelength, the DC bias operation point where the third-order intermodulation products of ~30dB and the following increase of spurious free dynamic range (SFDR) of ~20dB wave achieved in sub-octave narrow band operation.

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YBCO step-edge junction dc SQUID magnetometers with multi-loop pickup coil fabricated on sapphire substrates (사파이어 기판을 사용한 병렬 검출코일 구조의 계단형 모서리 접합 SQUID 자력계)

  • 황태종;김인선;김동호;박용기
    • Progress in Superconductivity
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    • v.5 no.2
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    • pp.94-97
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    • 2004
  • Step-edge Josephson junctions (SEJ) have been fabricated on sapphire substrates with in situ deposited films of CeO$_2$ buffer layer and YBa$_2$Cu$_3$O$_{7}$ films on the low angle steps. Direct coupled SQUID magnetometers with the SEJ were formed on 1 cm X 1 cm R-plane sapphire substrates. Typical 5-${\mu}{\textrm}{m}$-wide Josephson junctions have R$_{N}$ of 3 Ω and I$_{c}$ of 50 $mutextrm{A}$ at 77 K. The direct coupled SQUID magnetometers were designed to have pickup coils of 50-${\mu}{\textrm}{m}$-wide 16 parallel loops on the 1 cm X 1 cm substrates with outer dimension of 8.8 mm X 8.8 mm. The SEJ SQUID magnetometers exhibit relatively low 1/f noise even with dc bias control, and could be stably controlled by flux-locked loops in the magnetically disturbed environment. Field noise of the do SQUID was measured to be 200∼300 fT/Hz$^{1}$2/in the white noise region and about 2 pT/Hz$^{1}$2/ at 1 Hz when measured with dc bias method.hod.d.

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Low temperature deposition of LaMnO3 on IBAD-MgO template assisted by plasma (IBAD-MgO 기판상에 플라즈마를 이용한 LaMnO3 저온 증착)

  • Kim, H.S.;Oh, S.S.;Ha, D.W.;Ha, H.S.;Ko, R.K.;Moon, S.H.
    • Progress in Superconductivity and Cryogenics
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    • v.14 no.1
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    • pp.1-3
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    • 2012
  • LMO($LaMnO_3$) buffer layer of superconducting coated conductor was deposited on IBAD-MgO template in the plasma atmosphere at $650^{\circ}C$ which is relatively low compared with conventional deposition temperature of more than $800^{\circ}C$. Deposition method of LMO was DC sputtering, and target and deposition chamber were connected to the cathode and anode respectively. When DC voltage was applied between target and chamber, plasma was formed on the surface of target. The tape substrate was located with the distance of 10 cm between target and tape substrate. When anode bias was connected to the tape substrate, electrons were attracted from plasma in target surface to the tape substrate, and only tape substrate was heated by electron bombardment without heating any other zone. The effect of electron bombardment on the surface of substrate was investigated by increasing bias voltage to the substrate. We found out that the sample of electron bombardment had the effect of surface heating and had good texturing at low controlling temperature.

Rotor Initial Position Estimation Based on sDFT for Electrically Excited Synchronous Motors

  • Yuan, Qing-Qing;Wu, Xiao-Jie;Dai, Peng
    • Journal of Power Electronics
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    • v.14 no.3
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    • pp.564-571
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    • 2014
  • Rotor initial position is an important factor affecting the control performance of electrically excited synchronous motors. This study presents a novel method for estimating rotor initial position based on sliding discrete Fourier transform (sDFT). By injecting an ac excitation into the rotor winding, an induced voltage is generated in stator windings. Through this voltage, the stator flux can be obtained using a pure integral voltage model. Considering the influence from a dc bias and an integral initial value, we adopt the sDFT to extract the fundamental flux component. A quadrant identification model is designed to realize the accurate estimation of the rotor initial position. The sDFT and high-pass filter, DFT, are compared in detail, and the contrast between dc excitation and ac injection is determined. Simulation and experimental results verify that this type of novel method can eliminate the influence of dc bias and other adverse factors, as well as provide a basis for the control of motor drives.

Bipolar Pulse Bias Effects on the Properties of MgO Reactively Deposited by Inductively Coupled Plasma-Assisted Magnetron Sputtering

  • Joo, Junghoon
    • Applied Science and Convergence Technology
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    • v.23 no.3
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    • pp.145-150
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    • 2014
  • MgO thin films were deposited by internal ICP-assisted reactive-magnetron sputtering with bipolar pulse bias on a substrate to suppress random arcs. Mg is reactively sputtered by a bipolar pulsed DC power of 100 kHz into ICP generated by a dielectrically shielded internal antenna. At a mass flow ratio of $Ar/O_2$ = 10 : 2 and an ICP/sputter power ratio of 1 : 1, optimal film properties were obtained (a powder-like crystal orientation distribution and a RMS surface roughness of approximately 0.42 nm). A bipolar pulse substrate bias at a proper frequency (~a few kHz) prevented random arc events. The crystalline preferred orientations varied between the (111), (200) and (220) orientations. By optimizing the plasma conditions, films having similar bulk crystallinity characteristics (JCPDS data) were successfully obtained.

AC전압 인가에 따른 알루미늄 양극산화 공정 및 박막 특성

  • Lee, Jeong-Taek;Choe, Jae-Ho;Kim, Geun-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.242-242
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    • 2009
  • Fabrication of Anodic aluminum oxide under DC vias condition has been studied. When bias and time of anodic aluminum oxide process change, the hole distance and diameter size change. Comparison of fabricated AAO between AC vias and DC vias condition has been studied in this experiment. The first and second anodization of one aluminum is done by using DC and AC power supplier. And first and second anodization of another aluminum is done by DC power supplier. The size of the aluminum is $1cm{\times}3cm$, and second anodic aluminum oxide process takes about 45min. It is found that the hexagonal shape appears on the surface of the AAO. AC power source can fabricate aao which have a nano hole array. We can see that the hole on the surface of the AC vias has a better rounded hole than DC vias AAO. we need more data so we can get characteristic about AC power generated AAO.

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Bidirectional Current Triggering in Two-Terminal Planar Device Based on Vanadium Dioxide Thin Film Using 1550nm Laser Diode (1550nm 레이저 다이오드를 이용한 바나듐 이산화물 박막 기반 2단자 평면형 소자에서의 양방향 전류 트리거링)

  • Lee, Yong Wook
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.4
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    • pp.11-17
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    • 2015
  • While most switching devices are based on PN junctions, a single layer can realize a switching device in the case of vanadium dioxide($VO_2$) thin films. In this paper, bidirectional current triggering(switching) is demonstrated in a two-terminal planar device based on a $VO_2$ thin film by illuminating the film with an infrared laser at 1550nm. To begin with, a two-terminal planar device, which had a $30{\mu}m$-wide $VO_2$ conducting layer and an electrode separation of $10{\mu}m$, was fabricated. A specific bias voltage range for stable bidirectional laser triggering was experimentally obtained by measuring the current-voltage characteristics of the fabricated device in a current-controlled mode. Then, by constructing a test circuit composed of the device, a standard resistor, and a DC voltage source, connected in series, the transient response of laser-triggered current and its response time were investigated with a DC bias voltage, included in the above specific bias voltage range, applied to the device. In the test circuit with a DC voltage source of 3.35V and a $10{\Omega}$ resistor, bidirectional laser triggering could be realized with a maximum on-state current of 15mA and a switching contrast of ~78.95.

Etch Characteristics of CoTb and CoZrNb Thin Films by High Density Plasma Etching (고밀도 플라즈마 식각에 의한 CoTb과 CoZrNb 박막의 식각 특성)

  • Shin, Byul;Park, Ik Hyun;Chung, Chee Won
    • Korean Chemical Engineering Research
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    • v.43 no.4
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    • pp.531-536
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    • 2005
  • Inductively coupled plasma reactive ion etching of CoTb and CoZrNb magnetic materials with the photoresist mask was performed using $Cl_2/Ar$ and $C_2F_6/Ar$ gas mixtures and characterized in terms of etch rate and etch profile. As the concentrations of $Cl_2$ and $C_2F_6$ gases increased, the etch rates of magnetic films decreased and the etch slopes became slanted. The $Cl_2/Ar$ gas was more effective in obtaining fast etch rate and steep sidewall slope than the $C_2F_6/Ar$ gas. As the coil rf power and dc bias increased, fast etch rate and steep etch slope were obtained but the redeposition on the sidewall was observed. This is due to the increase of ion and radical densities in plasma with increasing the coil rf power and the increase of incident ion energy to the substrate with increasing the dc bias voltage. By applying high density reactive ion etching to magnetic tunnel junction stack containing various magnetic films and metal oxide, steep etch slope and clean etch profile without redeposition were obtained.

Analysis of the Gate Bias Effects of the Cascode Structure for Class-E CMOS Power Amplifier (CMOS Class-E 전력증폭기의 Cascode 구조에 대한 게이트바이어스 효과 분석)

  • Seo, Donghwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.6
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    • pp.435-443
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    • 2017
  • In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.