• Title/Summary/Keyword: DC protection relay

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A Study on High Impedance Grounding Protection for DC Power Supply System (DC 급전계통 고저항 지락보호에 대한 연구)

  • Lee, Kuk-Myoung;Kim, Byung-Hyun;So, Sun-Young;Kim, Hak-Lyun
    • Proceedings of the KSR Conference
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    • 2006.11b
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    • pp.878-884
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    • 2006
  • Grounding fault and short of the DC power supply systems are detected and protected by high-speed circuit breaker, linked breaking device, ground relay and fault selective device, all of which are installed and operated in substaions. however, there have been many cases in which the protective devices did not detect grounding of of the over head catenary systems on concrete support for an extended period of time. Such cases often cause severe damages to the supports with high grounding resistances. If grounding accidents occur repetitively, the earth current and the rise of earth potential can damage not only passenger and staff but also electric facilities and equipment, necessitating high cost and endeavor to restore. The following study points out various problems that can be occurred occur as a result of high impedance grounding accident, and proposes a new system which can protect and intercept them.

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A Protection Algorithm for DC Railway Systems Considering Train Starting (기동방식을 고려한 DC급전계통 보호알고리즘)

  • Kwon Y. J.;Choi D. M.;Kang S. H.;Han M. S.;Lee J. K.
    • Proceedings of the KIEE Conference
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    • summer
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    • pp.307-309
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    • 2004
  • A DC railway system has low feeder voltage, The remote fault current can be smaller than the current of load starting. So it is important to discriminate between the small fault current and the train starting current. The train starting current increases step by step but the fault current increases all at once. So the type of $\bigtriangleup I\;relay(50F)$ was developed using the different characteristics between the load starting current and the fault current. As for the train starting current, the time constant of train current at each step is much smaller than that of the fault current. To detect faults in U railway systems, an algorithm that is independent of train starting current. This algorithm use the time constant calculated by the method of least squares is presented in this paper.

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EMTP-RV Modeling of CT Saturation (EMTP-RV를 이용한 CT포화 모델링)

  • Kang, Yong-Cheol;Choi, Jae-Sun;Zheng, Tai-Ying;Kang, Hae-Gweon;Jang, Sung-Il;Kim, Yong-Gyun;Ryu, Young-Sik
    • Proceedings of the KIEE Conference
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    • 2008.11a
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    • pp.9-11
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    • 2008
  • A protection current transformer (CT) has been widely used for protection devices. When a fault occurs, a CT should provide the faithful reproduction of the primary fault current. However, a CT may saturates due to the magnitude of fault current, dc component primary time constant and the remanent flux of the iron core, and the secondary current of a CT is distorted. The distorted current can cause mal-operation or the operating time delay of a protection relay. This paper provides a modeling of CT saturation using EMTP-RV. The performance of the proposed CT saturation modeling was investigated under various fault conditions varying the fault distance, fault inception angle, and remanent flux of the iron core. The results indicate that the proposed EMTP-RV modeling can operate correctly, and the reasons for CT saturation are verified by EMTP-RV simulations.

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The Verification Method of Digital Protective Algorithm Using EMTDC (EMTDC를 이용한 Digital 보호 알고리즘 검증방법)

  • Lee, J.G.;An, B.S.;Jung, B.T.
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.674-676
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    • 1996
  • In this paper, we suggested the verification method of protective algorithms using EMTDC(Electro-Magnetic Transient DC). In other to verify protective algorithms using EMTDC, we first had to make a user defined component and then applied it to a simple power system with parallel line. By means of this method, We reduced the much time and effort to develop or improve the protective algorithm of digital protective relay. For the future, we apply this method to IDPACS(Integrated Digital Protection and Control System) and intend to implement more reliable digital protective relays.

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A Study on Operation Method of Protection Device for LVDC Distribution Feeder in Light Rail System (경전철용 LVDC 배전계통의 보호기기 운용 방안에 관한 연구)

  • Kang, Min-Kwan;Choi, Sung Sik;Lee, Hu-Dong;Kim, Gi-Yung;Rho, Dae-Seok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.20 no.4
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    • pp.25-34
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    • 2019
  • Recently, when a fault occurs at a long-distance point in a LVDC (low voltage direct current) distribution feeder in a light rail system, the magnitude of the current can decrease to less than that of the load current of a light rail system. Therefore, proper protection coordination method to distinguish a fault current from a load current is required. To overcome these problems, this paper proposes an optimal algorithm of protection devices for a LVDC distribution feeder in a light rail system. In other words, based on the characteristics of the fault current for ground resistance and fault location, this paper proposes an optimal operation algorithm of a selective relay to properly identify the fault current compared to the load current in a light rail system. In addition, this paper modelled the distribution system including AC/DC converter using a PSCAD/EMTDC S/W and from the simulation results for a real light rail system, the proposed algorithm was found to be a useful and practical tool to correctly identify the fault current and load current.

A FPGA Implementation of Digital Protective Relays for Electrical Power Installation (전력설비를 위한 디지털보호계전기의 FPGA 구현)

  • Kim, Jong-Tae;Shin, Myong-Chul
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.2
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    • pp.131-137
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    • 2005
  • Protective relays provide important features to electrical power systems for protecting against faults and consequent short circuits. This research presents a novel VLSI design of the digital protective relay, which overcomes today's uP/DSP-based relays. This design features good cancellation of DC/k-th harmonic components, noticeable not performance and flexible Protection behavior in the minimized core area The proposed design was successfully implemented by a FPGA(Field Programmable Gate Array) device and can concurrently process over 16KSPS at less $0.03[\%]$ error rate.

VHDL Design of High Performance FIR Filter for Digital Protection Relay Using Least Square Algorithm (최소자승 알고리즘을 이용한 디지털 보호 계전기용 고성능 FIR 필터의 VHDL 모델 설계)

  • Shin, Jae-Shin;Kim, Jong-Tae;Park, Jong-Kang;Seo, Jong-Wan;Shin, Myung-Cheol
    • Proceedings of the KIEE Conference
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    • 2003.07a
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    • pp.345-347
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    • 2003
  • 본 논문에서는 디지털 보호 계전기에 쓰이는 필터 중에서 최소 자승 알고리즘을 이용한 고성능 FIR 필터를 설계하였다. 기존의 DFT필터와 MATLAB 시뮬레이션을 이용하여 비교하였으며 FIR 필터의 VHDL모델 및 합성에 중점을 두었다. FIR 필터는 기본적으로 유한개의 임펄스 응답이 이루어지기 때문에 기타 다른 필터에 비하여 안정도가 높으며 선형적인 위상을 가지기 때문에 차단 주파수 대역의 왜곡현상을 없앨 수 있는 장점을 가지고 있다. 여러 가지 알고리즘으로 구현한 FIR 필터를 시뮬레이션 한 결과 최소 자승 알고리즘이 가장 우수한 결과를 나타내었다. 기본적으로 디지털 보호 계전기에서 디지털 필터의 기능은 사고 전압, 전류로부터 60Hz의 기본파 추출 CT, PT 왜곡 및 DC offset을 제거하는데 있다. 본 논문에서는 이러한 기능을 가지면서 샘플링 주파수와 차수를 같게 하여 FIR 필터와 DFT 필터의 주파수 응답과 연 산 속도를 비교 하였다. 본 논문에서 설계된 최소 자승 알고리즘을 이용한 FIR 필터는 같은 조건의 DFT필터에 비해 1고조파와 2고조파의 차이가 10db 이상 더 우수 하였으며 연산 속도 또한 2배 이상 좋은 결과를 보였다.

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