• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.492-501
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• 2013

In this paper, a multi polarization reconfigurable microstrip antenna that can be used selectively for four polarizations(vertical polarization, horizontal polarization, right hand circular polarization, left hand circular polarization) at the S-band is presented. The proposed antenna consists of four PIN diodes and a microstrip patch with a cross slot and a circular slot and is fed by utiliting electromagnetic coupling between the microstrip patch and the feed line. The proposed antenna has a DC bias network to supply DC voltage to each PIN diode and the polarization can be determined by controlling the ON /OFF states of four PIN diodes. The fabricated antenna has a VSWR below 2 in the vertical polarization(3.17~3.21 GHz), the horizontal polarization(3.16~3.20 GHz), the left hand circular polarization (3.08~3.19 GHz), and the right hand circular polarization(3.10~3.2 GHz) frequency bands. The designed antenna has the cross polarization level higher than 20 dB, a gain over 5 dBi for the linear polarization states, and 3 dB axial ratio bandwidth wider than 50 MHz in the circular polarization states.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1156-1163
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• 2006

This paper presents an ultra wideband(UWB) direct conversion mixer for IEEE 802.15.3a applications with simulation and measurement results. Since the direct conversion mixing causes dc-offset and even-order distortion, the proposed mixer adopts an anti-parallel diode pairs(APDPs) to solve these problems. The proposed mixer consists of an in-phase wilkinson power divider over $3.1{\sim}4.8GHz$, a wideband $45^{\circ}$ power divider over $1.5{\sim}2.4GHz$, and miniatured band pass filters(BPFs) for RF-LO isolations. The conversion loss is optimized with impedance matchings between APDPs and wideband components. The measured mixer shows the conversion loss of 13.5 dB, input third-order intercept-point($IIP_3$) of 7 dBm, and 1-dB gam compression point($P_{1dB}$) of -4 dBm. Quadrature(I/Q) outputs have the magnitude difference of about 1 dB and phase difference of ${\pm}3^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.183-190
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• 2007

This paper presents the design of 860 MHz band transmitter for improving power amplifier's linearity using Cartesian feedback method. For eliminating the effects of gain, phase mis-match, and DC offset, we estimate the property variations using ADS software. The implemented Cartesian feedback transmitter exhibits IMD3 of -54 dBc at an output power of 43 dBm and this result shows that the linearity is improved for 22.4 dB, compared with the test of the power amplifier without Cartesian feedback system. Thus, we verify that the proposed Cartesian feedback transmitter can be applied to narrow-band transmitter systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.400-405
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• 2023

Currently, inverted pendulums are being studied in many fields, including posture control of missiles, rockets, etc, and bipedal robots. In this study, the vertical posture control of the pendulum was studied by constructing a rotary inverted pendulum using a 256-pulse rotary encoder and a DC motor. In the case of nonlinear systems, complex algorithms and controllers are required, but a control method using the classic and relatively simple PID(Proportional Integral Derivation) algorithm was applied to the rotating inverted pendulum system, and a simple but desired method was studied. The rotating inverted pendulum system used in this study is a nonlinear and unstable system, and a PID controller using Microchip's dsPIC30F4013 embedded processor was designed and implemented in linear modeling. Usually, PID controllers are designed by combining one or two or more types, and have the advantage of having a simple structure compared to excellent control performance and that control gain adjustment is relatively easy compared to other controllers. In this study, the physical structure of the system was analyzed using mathematical methods and control for vertical balance of a rotating inverted pendulum was realized through modeling. In addition, the feasibility of controlling with a PID controller using a rotating inverted pendulum was verified through simulation and experiment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.47-55
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• 2012

A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5796-5800
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• 2014

This paper presents reconfigurable beam steering patch antenna with high gain for a wireless headset. Because existing antenna for wireless communication in headsets has an omni-directional radiation pattern, it has a deleterious effect in the vicinity of the human head. To reduce this effect, this paper proposed an antenna comprised of a U-slot and manufactured on a FR-4 substrate. The antenna operating at the 2.37-2.5 GHz band used a tapered matching method to match the impedance between the feed part and patch part. To implement the beam steering capability, the antenna used two PIN diodes. Using PIN diodes, the antenna presented three states ($S_0$, $S_1$ and $S_2$) in the maximum beam directions of the YZ-plane ($0^{\circ}$, $30^{\circ}$ and $330^{\circ}$, respectively). The peak gains of the antenna in the headset were 4.22-5.15 dBi. The fabricated antenna could communicate efficiently with a wireless headset.

• Journal of Navigation and Port Research
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• v.27 no.2
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• pp.209-215
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• 2003

In this paper. We tested and fabricated the error amplifier for the 15 Watt linear power amplifier for the IMT-2000 baseband station. The error amplifier was comprised of subtractor for detecting intermodulation distortion, variable attenuator for control amplitude, variable phase shifter for control phase, low power amplifier and high power amplifier. This component was designed on the RO4350 substrate and integrated the aluminum case with active biasing circuit. For suppression of spurious, the through capacitance was used. The characteristics of error amplifier measured up to 45 dB gain, $\pm$0.66 dB gain flatness and -15 dB input return loss. Results of application to the 15 Watt feedforward Linear Power Amplifier, the error amplifier improved with 27 dB cancellation from 34 dBc to 61 dBc IM$_3$.

• Journal of Navigation and Port Research
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• v.27 no.1
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• pp.81-86
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• 2003

In the paper, the power amplifier using active biasing for LDMOS MRF-21060 is designed and fabricated. Driving amplifier using AH1 and parallel power amplifier AH11 is made to drive the LDMOS MRF 21060 power amplifier. The variation of current consumption in the fabricated 5 Watt power amplifier has an excellent characteristics of less than 0.1A, whereas passive biasing circuit dissipate more than 0.5A. The implemented power amplifier has the gain over 12 dB, the gain flatness of less than $\pm$0.09dB and input and output return loss of less than -19dB over the frequency range 2.11~2.17GHz. The DC operation point of this power amplifier at temperature variation from $0^{\circ}C$ to $60^{\circ}C$ is fixed by active circuit.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.