• 한국지능시스템학회논문지
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• 제25권3호
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• pp.299-305
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• 2015

Global environmental concerns and the ever increasing need of energy, coupled with steady progress in renewable energy technologies, are opening up new opportunities for utilization of renewable energy resources. Distributed electricity generation is a suitable option for sustainable development thanks to the load management benefits and the opportunity to provide electricity to remote areas. Solar energy being easy to harness, non-polluting and never ending is one of the best renewable energy sources for electricity generation in present and future time. Due to the random and intermittent nature of solar source, PV plants require the adoption of an energy storage and management system to compensate fluctuations and to meet the energy demand during night hours. This paper presents an efficient, economic and technical model for the design of a MPPT based grid connected PV with battery storage and management system. This system satisfies the energy demand through the PV based battery energy storage system. The aim is to present PV-BES system design and management strategy to maximize the system performance and economic profitability. PV-BES (photovoltaic based battery energy storage) system is operated in different modes to verify the system feasibility. In case of excess energy (mode 1), Li-ion batteries are charged using CC-CV mechanism effectively controlled by fuzzy logic based PID control system whereas during the time of insufficient power from PV system (mode 2), batteries are used as backup to compensate the power shortage at load and likewise other modes for different scenarios. This operational mode change in PV-BES system is implemented by State flow chart technique based on SOC, DC bus voltages and solar Irradiance. Performance of the proposed PV-BES system is verified by some simulations study. Simulation results showed that proposed system can overcome the disturbance of external environmental changes, and controls the energy flow in efficient and economical way.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.158-163
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• 2005

Competitive electricity markets necessitate equitable methods for allocating transmission usage in order to set transmission usage charges and congestion charges in an unbiased and an open-accessed basis. So in competitive markets it is usually necessary to trace the contribution of each participant to line usage, congestion charges and transmission losses, and then to calculate charges based on these contributions. A UPFC offers flexible power system control, and has the powerful advantage of providing, simultaneously and independently, real-time control of voltage, impedance and phase angle, which are the basic power system parameters on which sys-tem performance depends. Therefore, UPFC can be used efficiently and flexibly to optimize line utilization and increase system capability and to enhance transmission stability and dampen system oscillations. In this paper, a mathematical approach to allocate the contributions of system users and UPFCs to transmission system usage is presented. The paper uses a dc-based load flow modeling of UPFC-inserted transmission lines in which the injection model of the UPFC is used. The relationships presented in the paper showed modified distribution factors that modeled impact of utilizing UPFCs on line flows and system usage. The derived relationships show how bus voltage angles are attributed to each of changes in generation, injections of UPFC, and changes in admittance matrix caused by inserting UPFCs in lines. The relationships derived are applied to two test systems. The results illustrate how transmission usage would be affected when UPFC is utilized. The relationships derived can be adopted for the purpose of allocating usage and payments to users of transmission network and owners of UPFCs used in the network. The relationships can be modified or extended for other control devices.

• Journal of Power Electronics
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• 제16권5호
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• pp.1950-1963
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• 2016

A novel open-circuit fault diagnosis method for 3-phase 4-wire 3-level active power filters based on voltage error correlation is proposed in this paper. This method is based on observing the output pole voltage error of the active power filter through two kinds of algorithms. One algorithm is a voltage error analytical algorithm, which derives four output voltage error analytic expressions through the pulse state, current value and dc bus voltage, respectively, assuming that all of the IGBTs of a certain phase come to an OC fault. The other algorithm is a current circuit equation algorithm, which calculates the real-time output voltage error through basic circuit theory. A correlation is introduced to measure the similarity of the output voltage errors between the two algorithms, and OC faults are located by the maximum of the correlations. A FPGA has been chosen to implement the proposed method due to its fast prototyping. Simulation and experimental results are presented to show the performance of the proposed OC fault diagnosis method.

• Journal of Electrical Engineering and Technology
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• 제7권1호
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• pp.1-8
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• 2012

The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

• 정보처리학회논문지D
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• 제17D권1호
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• pp.41-52
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• 2010

생성된 테스트 케이스와 요구사항과의 연관관계가 중요하지만, 모델을 이용한 테스트 케이스 자동생성에서는 모델이 요구사항과 m:n의 관계를 맺기 때문에 테스트 케이스와 요구사항과의 관계도 매우 복잡해진다. 본 논문에서는 1:1 모델링 도구인 REED(REquirement EDitor)를 이용하여 테스트 케이스를 생성하는 방법에 대하여 기술한다. 테스트 케이스는 커버리지 타겟 생성, IORT(Input Output Relation Tree) 생성, 테스트 케이스 생성의 3단계를 거치며, 모든 단계는 자동으로 진행된다. 생성된 테스트 케이스는 하나의 요구사항에서 생성될 수 있으며 실제 시스템에 적용한 결과, 온도조절장치 경우는 5,566개, 버스카드 단말기의 경우는 3,757개, 굴착기 제어기는 4,611개의 테스트 케이스가 생성되었다.

• 조명전기설비학회논문지
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• 제16권3호
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• pp.74-83
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• 2002

본 논문은 전력설비에 조기적용이 예상되는 초전도한류기의 파라메타를 정의하고 앞으로 개발방향을 제시하기 위하여 한류기의 동작원리, 특성 및 계통조기적용가능성들을 근거로 파라메타의 특성을 비교 ·평가하였다. 또한 한류기의 계통적용효과를 분석하기 위하여 SFCL이 기간 특고압 모델계통에 도입한 경우를 상정하여 3선지락 고장에서 저항형과 유도형 SFCL의 도입 효과에 대하여 RTDS (Real Time Digital Simulation)/EMTDC(Electromagnetic Transient DC)로 시뮬레이션하였다. 특히 저항형과 유도형의 한류효과의 비교 평가, 모선전압의 저하 억제 및 계통과 한류기의 파라메타와의 관련성에 대하여 검토하였다.

• Smart Structures and Systems
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• 제2권2호
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• pp.115-126
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• 2006

The Terra-Scope system is an affordable 4-D down-hole seismic monitoring system based on independent, microprocessor-controlled sensor Pods. The Pods are nominally 50 mm in diameter, and about 120 mm long. They are expected to cost approximately $6000 each. An internal 16-bit, extremely low power MCU controls all aspects of instrumentation, eight programmable gain amplifiers, and local signal storage. Each Pod measures 3-D acceleration, tilt, azimuth, temperature, and other parametric variables such as pore water pressure and pH. Each Pod communicates over a standard digital bus (RS-485) through a completely web-based GUI interface, and has a power consumption of less than 400 mW. Three-dimensional acceleration is measured by pure digital force-balance MEMS-based accelerometers. These accelerometers have a dynamic range of more than 115 dB and a frequency response from DC to 1000 Hz with a noise floor of less than $30ng_{rms}/{\surd}Hz$. Accelerations above 0.2 g are measured by a second set of MEMS-based accelerometers, giving a full 160 dB dynamic range. This paper describes the system design and the cooperative shared-time scheduler implemented for this project. Restraints accounted for include multiple data streams, integration of multiple free agents, interaction with the asynchronous world, and hardened time stamping of accelerometer data. The prototype of the device is currently undergoing evaluation. The first array will be installed in the spring of 2006.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권6호
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• pp.2168-2187
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• 2021

The smart grid replaces the traditional power structure with information inventiveness that contributes to a new physical structure. In such a field, malicious information injection can potentially lead to extreme results. Incorrect, FDI attacks will never be identified by typical residual techniques for false data identification. Most of the work on the detection of FDI attacks is based on the linearized power system model DC and does not detect attacks from the AC model. Also, the overwhelming majority of current FDIA recognition approaches focus on FDIA, whilst significant injection location data cannot be achieved. Building on the continuous developments in deep learning, we propose a Deep Learning based Locational Detection technique to continuously recognize the specific areas of FDIA. In the development area solver gap happiness is a False Data Detector (FDD) that incorporates a Convolutional Neural Network (CNN). The FDD is established enough to catch the fake information. As a multi-label classifier, the following CNN is utilized to evaluate the irregularity and cooccurrence dependency of power flow calculations due to the possible attacks. There are no earlier statistical assumptions in the architecture proposed, as they are "model-free." It is also "cost-accommodating" since it does not alter the current FDD framework and it is only several microseconds on a household computer during the identification procedure. We have shown that ANN-MLP, SVM-RBF, and CNN can conduct locational detection under different noise and attack circumstances through broad experience in IEEE 14, 30, 57, and 118 bus systems. Moreover, the multi-name classification method used successfully improves the precision of the present identification.

• 한국진공학회지
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• 제16권6호
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• pp.483-488
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• 2007

KSTAR (Korea Superconducting Tokamak Advanced Research) 전류전송계 (Current Feeder System)는 4.5 K의 저온에서 운전되는 초전도자석과 300 K의 실온에서 운전되는 전원장치 (Magnet Power Supply)를 전기적으로 연결하는 장치이다. 전류전송계는 최대 35 kA의 DC 전류가 인가되는 TF 자석용 및 350초간 20$\sim$26 ㎄의펄스 전류가 인가되는 PF 자석용으로 분리되어 있으며 리드박스 내부는 전류인입선, 초전도버스라인, 열차폐체 및 냉각라인 등이 설치되어 있다. 리드박스와 초전도버스라인 진공덕트는 KSTAR 주장치와는 별도로 진공배기 시스템이 구축되어있으며, 전체적으로 아령 형상을 하고 있는 진공공간을 효율적으로 진공배기하기 위하여 버스라인 덕트와 주장치 저온용기 사이에 진공 분리막 (Vacuum Separator)이 설치되어 있다. 진공배기를 위한 초벌배기계는 로터리펌프 및 부스터펌프 (Mechanical Booster Pump)로 구축되었으며 고진공 배기계는 4대의 크라이오펌프 (Cryo-pump)로 구축되었다. 진공장치 운전을 위해 PLC 기반의 로컬 제어시스템을 구축하였고 장치 안전을 위한 자체 인터록과 중앙인터록 시스템 및 중앙제어연계시스템이 함께 구축되어 있다. 전류전송계 설치완료 후 진공배기 시운전을 통해 배기시스템의 자가진단 및 리드박스 내부에 설치되어 있는 헬륨배관의 진공누설검사를 완료하였으며, 액체질소를 사용하여 전류인입선 냉각시험을 완료하였다.

• 천문학논총
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• 제21권2호
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).