• Title/Summary/Keyword: DC/DC power conversion

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Fabrication of Cu2SnS3 (CTS) thin Film Solar Cells by Sulfurization of Sputtered Metallic Precursors (스퍼터법을 이용한 메탈 전구체기반의 Cu2SnS3 (CTS) 박막 태양전지 제조 및 특성 평가)

  • Lee, Ju Yeon;Kim, In Young;Minhao, Wu;Moon, Jong Ha;Kim, Jin Hyeok
    • Current Photovoltaic Research
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    • v.3 no.4
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    • pp.135-139
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    • 2015
  • $Cu_2SnS_3$ (CTS) based thin film solar cells (TFSCs) are of great interest because of its earth abundant, low-toxic and eco-friendly material with high optical absorption coefficient of $10^4cm^{-1}$. In this study, the DC sputtered precursor thin films have been sulfurized using rapid thermal annealing (RTA) system in the graphite box under Ar gas atmosphere for 10 minute. The systematic variation of sulfur powder during annealing process has been carried out and their effects on the structural, morphological and optical properties of CTS thin films have been investigated. The preliminary power conversion efficiency of 1.47% with a short circuit current density of $33.9mA/cm^2$, an open circuit voltage of 159.7 mV, and a fill factor of 27% were obtained for CTS thin film annealed with 0.05g of S powder, although the processing parameter s have not yet been optimized.

The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter (10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계)

  • Chung, Kang-Min
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.195-202
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    • 2004
  • This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

60 GHz CMOS SoC for Millimeter Wave WPAN Applications (차세대 밀리미터파 대역 WPAN용 60 GHz CMOS SoC)

  • Lee, Jae-Jin;Jung, Dong-Yun;Oh, Inn-Yeal;Park, Chul-Soon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.670-680
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    • 2010
  • A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

MIMIC 94 GHz high isolation single balanced cascode mixer (94 GHz 대역의 높은 격리 특성의 MIMIC single balanced cascode 믹서)

  • Lee, Sang-Jin;An, Dan;Lee, Mun-Kyo;Moon, Sung-Woon;Bang, Suk-Ho;Baek, Tae-Jong;Kwon, Hyuk-Ja;Jun, Byoung-Chul;Yoon, Jin-Seob;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.25-33
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    • 2007
  • In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.