• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.79-81
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• 2020

임계모드 (Critical conduction mode, CrM) 동작을 하는 PFC 컨버터는 주파수 변동을 통한 Valley switching 동작으로 인하여 높은 효율 및 양호한 EMI 특성을 가진다. 하지만 Peak 부하가 큰 시스템에서 CrM 설계를 하게 되면 정격부하에서 비교적 높은 주파수의 동작이 불가피하여 시스템 효율이 나빠지고 높은 DC-bias 확보를 위해 인덕터 크기가 커지게 된다. 따라서 본 논문에서는 고효율 및 인덕터 사이즈 저감을 위한 임계모드에서 동작하는 두 개의 교차형 PFC 컨버터의 병렬 구동에 대해서 이야기하고자 한다.

• Journal of Sensor Science and Technology
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• v.7 no.6
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• pp.401-408
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• 1998

A dual-channel automatic ac-dc voltage transfer error measurement system in which the output voltages of two thermal voltage converters which are ac voltage standard are directly measured at the same time to reduce the output voltage drift is described. Forward-reverse measurement method by using a two-channel scanner is used to cancel the offset voltage of the voltmeters. The agreements of the 4-V TVC comparison results between other national standards institute and Korea Research Institute of Standards and Science were less than about ${\pm}2\;ppm$ in the frequency range of $40\;Hz{\sim}100\;kHz$, and were less than about ${\pm}4\;ppm$ at $200\;kHz{\sim}1\;MHz$. Measurement uncertainty is reduced significantly from ${\pm}4\;ppm$ of manual system to ${\pm}3\;ppm$ of new system(up to 100 kHz) typically and great increase in comparison efficiency has been achieved by this system.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.433-440
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• 2007

Recently, the reduction of standby power consumption is significantly issued in electronic and electrical industry for the conservation of environment. In the case of a switched mode power supply (SMPS), it is demanded high efficiency at extremely low output power conditions by consumers. However, it is very different from high efficiency techniques at full load conditions. In addition, many SMPSs are designed as a multi-output circuit for various loads because of cost down. This circuit is difficult to implement both high efficiency and good cross regulation performance, simultaneously. In this paper, secondary side post regulator (SSPR), current mode control method, and power sequence control technique are proposed to reduce standby power consumption and to improve cross regulation performance of the multi-output SMPSs which consist of single or multiple converter. The proposed methods are analyzed by their operational principles and optimal designs verified by experimental results with 110[W] and 270[W] SMPSs.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.143-153
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• 2014

This paper presents a novel application of LCC resonant converter for 60kW EV fast charger and describes development of the high efficiency 60kW EV fast charger. The proposed converter has the advantage of improving the system efficiency especially at the rated load condition because it can reduce the conduction loss by improving the resonance current shape as well as the switching loss by increasing lossless snubber capacitance. Additionally, the simple gate driver circuit suitable for proposed topology is designed. Distinctive features of the proposed converter were analyzed depending on the operation modes and detail design procedure of the 10kW EV fast charger converter module using proposed converter topology were described. The proposed converter and the gate driver were identified through PSpice simulation. The 60kW EV fast charger which generates output voltage ranges from 50V to 500V and maximum 150A of output currents using six parallel operated 10kW converter modules were designed and implemented. Using 60kW fast charger, the charging experiments for three types of high-capacity batteries were performed which have a different charging voltage and current. From the simulation and experimental results, it is verified that the proposed converter topology can be effectively used as main converter topology for EV fast charger.

• Journal of Sensor Science and Technology
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• v.9 no.4
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• pp.288-296
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• 2000

Thin-film chromel-alumel multijunction thermal converters with a low output resistance of $64{\sim}85\;{\Omega}$ showed approximately the square law-dependent input-output relation. The voltage responsivities were very low with $0.34{\sim}0.67\;V/W$ in air and $1.15{\sim}1.48\;V/W$ in vacuum, respectively, and the ac-dc voltage transfer error was very large with about +340 ppm in the frequency range of $40\;Hz{\sim}10\;kHz$ in the case of 1 V-input sinewave rms voltage. It can be concluded that the large transfer error of the thermal converter was mainly caused by the low voltage responsivity and the large heat loss due to low output resistance, which implies that the optimization for small ac-dc transfer error is required.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.608-618
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• 2004

In this paper, modifying the diode star double balanced mixer of Maas, a novel resistive 60 GHz pHEMT MMIC star mixer is suggested. Due to star configuration, troublesome IF balun for ring configuration FET mixer is not necessary. In addition, the sysematic design method of dual balun through EM simulation is suggested rather than the design by inspection as Maas. The mixer circuit is fabricated as MMIC on CPW base using 0.1 um GaAs pHEMT Library of MINT in Dongguk University. The size is 1.5 ${\times}$ 1.5 $\textrm{mm}^2$ and its performance is adjustable by DC supply. It can be operated as both up and down converters and it shows the conversion loss of about 13∼18 ㏈ over the full V-band frequencies.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1886-1900
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• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1108-1121
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• 2019

The non-inverting buck-boost converter (NIBB) is a step-up and step-down DC-DC converter suitable for wide-input-voltage-range applications. However, when the input voltage is close to the output voltage, the NIBB needs to operate in the buck-boost mode, causing a significant efficiency reduction since all four switches operates in the PWM mode. Considering both the current stress limitation and the efficiency optimization, a novel design methodology for the optimal phase-shift modulation of a NIBB in the buck-boost mode is proposed in this paper. Since the four switches in the NIBB form two bridges, the shifted phase between the two bridges can serve as an extra degree of freedom for performance optimization. With general phase-shift modulation, the analytic current expressions for every duty ratio, shifted phase and input voltage are derived. Then with the two key factors in the NIBB, the converter efficiency and the switch current stress, taken into account, an objective function with constraints is derived. By optimizing the derived objective function over the full input voltage range, an offline design methodology for the optimal modulation scheme is proposed for efficiency optimization on the premise of current stress limitation. Finally, the designed optimal modulation scheme is implemented on a DSPs and the design methodology is verified with experimental results on a 300V-1.5kW NIBB prototype.

• Journal of Power Electronics
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• v.19 no.4
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• pp.846-857
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• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.