• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.2
• /
• pp.333-340
• /
• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.6A
• /
• pp.519-536
• /
• 2007

In this paper, we combine the Hybrid-Automatic Repeat reQuest (HARQ) algorithm with joint Tx and Rx antenna selection based on the reliability of the individual antennas links. The cyclic redundancy check (CRC) is applied on the data before being encoded using the Turbo encoder. In the receiver the CRC is used to detect errors of each antenna stream and to decide whether a retransmission is required or not. The receiver feeds back the transmitter with the Tx antennas ordering and the acknowledgement of each antenna (ACK or NACK). If the number of ACK antennas is higher than the NACK antennas, then the retransmission takes place from the ACK antennas using the Chase Combining (CC). If the number of the NACK antennas is higher than the ACK antennas then the ACK antennas are used to retransmit the data streams using the CC algorithm and additional NACK antennas are used to retransmit the remaining streams using Incremental Redundancy (IR, i.e. the encoder rate is reduced). Furthermore, the HARQ is used with the I-BLAST (Iterative-BLAST) which grantees a high transmission rate.

• Journal of the Korean Society for Railway
• /
• v.8 no.1
• /
• pp.1-5
• /
• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.57-64
• /
• 2011

To adjust the difference of bandwidth between host interface and NAND flash memory, DRAM is adopted as the buffer management in SSD (Solid-state Disk). In this paper, we propose cost-effective techniques to enhance SSD performance instead of using expensive high bandwidth DRAM. The SSD data can be classified into three groups such as user data, meta data for handling user data, and FEC(Forward Error Correction) parity/ CRC(Cyclic Redundancy Check) for error control. In order to improve the performance by considering the features of each data, we devise a flexible burst control method through monitoring system and a page based FEC parity/CRC application. Experimental results show that proposed methods enhance the SSD performance up to 25.9% with a negligible 0.07% increase in chip size.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3C
• /
• pp.195-204
• /
• 2007

The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.1
• /
• pp.109-117
• /
• 2013

Polar codes are the first provable error correcting code achieving the symmetric channel capacity in a wide case of binary input discrete memoryless channel(BI-DMC). However, finite length polar codes have an error floor problem with successive-cancellation list(SCL) decoder. From previous works, we can solve this problem by concatenating CRC(Cyclic Redundancy Check) codes. In this paper we propose to make polar codes having extended-minimum distance from original polar codes without outer codes using correlation with generate matrix of polar codes and that of RM(Reed-Muller) codes. And we compare performance of proposed polar codes with that of polar codes concatenating CRC codes.

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.896-900
• /
• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• Proceedings of the IEEK Conference
• /
• 2003.07a
• /
• pp.533-536
• /
• 2003

본 논문에서는 전화선을 이용한 고속 홈네트워크인 HomePNA 2.0 시스템에서 HomePNA 2.0 (H2) 프레임을 만들기 위한 프레임 프로세싱 중, 다항식 나누기 연산을 통한 CRC (Cyclic Redundancy Check) 16비트 생성, HCS (Header Check Sequence) 8비트 생성 및 혼화(Scrambling) 처리에 있어서 입력 8 비트를 동시에 병렬 처리함으로써 기존의 1 비트 입력을 LFSR (Linear Feedback Shift Register)를 사용한 다항식 나누기 연산을 수행했을 때보다 빠른 속도로 H2 프레임을 구현하고자 하는 고속 처리 기법을 제시하고 이의 성능을 검증하였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.07a
• /
• pp.460-462
• /
• 2005

본 논문은 통신 시스템에서 오류 검출을 위해 널리 사용되고 있는 Cyclic Redundancy Check (CRC)회로의 병렬 구현을 위한 최적화 알고리즘을 제시한다. 논리 단을 최소로 하면서 가능한 않은 공유 텀을 찾아 매핑 함으로써 속도 및 게이트 수를 줄인다. 본 논문에서는 이더넷의 32비트 CRC를 병렬로 구현하여 성능평가를 하였다. FPGA 및 표준 셀 라이브러리를 이용하여 합성하였으며, 기존의 방식에 비해 속도와 면적 모두 향상되었음을 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.9C
• /
• pp.848-854
• /
• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handhold systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one in AWGN channel and TI channel.