• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.201-202
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• 2012

This paper presents a simple and cost-effective stand-alone rapid battery charging system of 30kW for electric vehicles. The proposed system mainly consists of active front-end rectifier of neutral point clamped 3-level type and non-isolated bi-directional dc-dc converter of multi-phase interleaved half-bridge topology. The charging system is designed to operate for both lithium-polymer and lithium-ion batteries. The complete charging sequence is made up of three sub-interval operating modes; pre-charging mode, constant-current mode, and constant-voltage mode. Each mode is operated according to battery states: voltage, current and State of Charging (SOC). The proposed system is able to reach the full-charge state within less than 16min for the battery capacity of 8kWh by supplying the charging current of 67A. The optimal discharging algorithm for Vehicle to the Grid (V2G) operation has been adopted to maintain the discharging current of 1C. Owing to the simple and compact power conversion scheme, the proposed solution has superior module-friendly mechanical structure which is absolutely required to realize flexible power expansion capability in a very high-current rapid charging system. Experiment waveforms confirm the proposed functionality of the charging system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.540-547
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• 2004

In this paper, a current - mode class D(CMCD) power amplifier over 70 % power added efficiency at 900 ㎒ is designed and implemented. Based on push-pull class B structure, main power loss due to charge and discharge of output capacitance in switching mode power amplifier is minimized by applying a parallel harmonic control circuit. Experimental CMCD amplifier with 73 % power added efficiency at 3.2 W and 72 % power added efficiency at 5 W are achieved respectively. In addition a characteristic of switching mode power amplifier whose output power is proportional to magnitude of U power is verified.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1064-1070
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• 2007

This paper presents a grid-interactive current controlled voltage source inverter (CCVSI) with uniterruptible power supply (UPS), which uses an inner current control loop (polarized ramp time (PRT)) and outer feedback control loops to improve grid power quality and UPS. To reduce the complexity, cost and number of power conversions, which results in higher efficiency, a single stage CCVSI is used. The operation of this system could be divided into the power quality control (PQC) state mode and the UPS state mode. In PQC mode, the system operated to compensate the reactive power demand by nonlinear load or variation in load. In UPS mode. the system is controlled to provide a sinusoidal voltage at the rated value for the load when the gird fail. To verify the proposed system, a comprehensive evaluation with theoretical analysis, simulation and experimental results for 1KVA load capacity is presented.

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.104-110
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• 2011

High-brightness LED control is required for stable operation, thus the driver and control system must be designed to deliver a constant current to optimize reliability and ensure consistent luminous flux. In this paper, the sliding mode current controller is designed to adjust the illumination density of power LEDs. The controller design model of power LEDs, including its driving circuit, is proposed to realize the dimming control of power LEDs. A buck converter is introduced to drive the power LEDs and reduce the input voltage to a lower level. The sliding mode software controller is implemented to adjust the dimming of power LEDs. The proposed strategy for driving power LEDs is investigated and comparatively studied by experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.6
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• pp.507-514
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• 2013

In this paper, the proposed charging algorithm is converted from the charging mode to compensate the transient state in the solar battery charging system. The maximum power point tracking (MPPT) control methods and the various charging algorithms for the optimal battery charging are reviewed. The proposed algorithm has excellent transient characteristics compare to the previous algorithm by adding the optimal control method to compensate the transient state when the charging mode switches from the constant current mode to the constant voltage mode based on the conventional constant-current constant-voltage (CC-CV) charging algorithm. The effectiveness of the proposed method has been verified by simulations and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.5
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• pp.479-488
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• 1991

A novel three-phase quasi-resonant dc link inverter (QRI)with a switch connected between dc voltage source and resonant inductor is proposed. According to the state of switching and load current, the operating mode of the proposed inverter scheme is classified into free-wheeling, inverting, and rectifying mode. By examining the behavior of the circuit in each operating mode, an equivalent circuit which represents all the modes in a unified manner is derived. The operating principle of QRI at inverting mode is analyzed, and it is shown that the maximum voltage of resonant dc link is confined to twice the dc source voltage and that both the zero voltage switching of inverter and the zero current switching of inserted switch are guaranteed. An appropriate current control algorithm is suggested, and the opeating characteristics of proposed resonant inverter are verified through both simulation and experiment.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.355-358
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• 2008

In the current GPON market and standard, the line bit rate requirement is changing from 1.25 Gbps to 2.5 Gbps. We fabricate a 2.5 Gbps burst-mode receiver with commercially available blocks and optimize it with an APD bias control. A burst-mode measurement setup is made for the full compliance test with the GPON standard. The device meets the partially defined 2.5 Gbps specs in the current ITU G.984.2 standard, also, supports 1.25 Gbps specs for the coexistence issue in an access network. The full-compliant measurement values can be used as a guideline for fixing "for further study" specs in the current GPON standard at 2.5 Gbps.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.207-214
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• 2019

In this study, discrete-time domain analysis is proposed to investigate the input current of a buck AC/DC light-emitting diode (LED) driver. The buck power factor correction converter can operate in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Two discontinuous and two continuous conduction operating modes are possible depending on which event terminates the conduction of the main switch in a switching cycle. All four operating modes are considered in the discrete-time domain analysis. The peak current-mode control with slope compensation is used to design a low-cost AC/DC LED driver. A slope compensation design of the buck AC/DC LED driver is described on the basis of a discrete-time domain analysis. Experimental results are presented to confirm the usefulness of the proposed analysis.