• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Transactions on Electrical and Electronic Materials
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• v.4 no.6
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Proceedings of the IEEK Conference
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• summer
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.102-105
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• 1997

The thickness dependence of stress voltage oxide currents has been measured in oxides with thicknesses between 10nm and 80nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was caused by trap assited tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.3
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• pp.411-418
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• 1998

The thickness dependence of stress electric filed oxide currents has been measured in oxides with thicknesses between 10 nm and 80 nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was composed of stress induced leakage current and dc current. The stress current was caused by trap assisted tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.371-371
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• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of East-West Nursing Research
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• v.12 no.1
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• pp.43-55
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• 2006

Purpose: This study was a descriptive study to assess the relationships between acculturative stress and current perception of stress in Korean immigrants. Methods: The subjects consisted of 154 community-dwelling Korean immigrant living in the USA. Data collection was conducted through the use of questionnaires. The instruments for this study were Acculturative stress (12 items), The Global Assessment of Recent Scale(8 items). The collected data were analysed using SPSS PC 12.0 Programme for Frequency, Percentage, t-test, ANOVA, Duncan test and Pearson's correlation coefficient according to the purpose of this study. Results: 1) The average item score for acculturative stress was 17.17. The average item score for current perception of stress was 26.56. 2) Acculturative stress was positively related to current perception of stress (r=.360, p<.01). 3) Acculturative stress was significantly different according to educational level (F=2.709, p=.047), occupation (F=16.202, p=.000), perceived income comfort level (F=26.666, p=.000), and type of residence (F=2.672, p=.050). The Current perception of stress was significantly different according to age (F=7.380, p=.000), marital status (F=5.354, p=.006), perceived income comfort level (F=12.738, p=.000), and type of residence(F=4.207, p=.007). Conclusion: Theses findings help to clarify relationships between acculturative stress and current perception of stress in Korean immigrants. Therefore, the result of study provide clues for the quality of life of Korean immigrants.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.