• 대한전기학회논문지:전력기술부문A
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• 제48권6호
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• pp.807-814
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• 1999

In this paper, it is shown that high frequency current can be controlled to concentrate near the desired path in a conducting plate. A conducting plate is modelled to examine current distribution. And current distribution is analyzed in view of the frequency and geometric characteristics of current path. The high frequency current behavior from the analysis is compared with the experiments. The results, obtained by the experiments of test specimens, are in good agreement with the analytical results.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2008년도 학술대회 1부
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• pp.298-303
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• 2008

사용자의 과거 이동 경로 자료는 사용자의 현재 이동 위치를 예측하고 이외 관련된 서비스를 제공하는데 유용하게 사용될 수 있다. 본 논문에서는 사용자의 과거 이동 경로의 분석을 통하여 이동 중인 사용자의 시공간 위치예측 기술을 제안한다. 환경으로부터 발생한 사용자의 이동 경로를 수집하고 수집된 데이터에서 이동 경로 요약(Path Summarization)과 이동 경로 선택(Path Selection) 방법을 제안한다. 이동 경로 요약 방법은 환경으로부터 수집한 사용자의 이동 경로를 군집 분류하고, 이동 경로 선택 방법은 이동 중에 발생한 경로의 거리, 시간, 방향의 요소와 동적 정합법을 사용하여 유사성(Similarity)을 측정하며 유사성이 가장 높은 경로를 선택한다. 선택된 경로는 시간에 따른 공간 정보 빚 위치에 따른 시간 예측 서비스를 위하여 사용가능 하며, 실험을 통하여 유사성이 높은 이동 경로를 선택하는 모습을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권3호
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• pp.490-508
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• 2013

One of the most important scalability issues facing the current Internet is the rapidly increasing rate of BGP updates (BGP churn), to which route flap and path exploration are the two major contributors. Current countermeasures would either cause severe reachability loss or delay BGP convergence, and are becoming less attractive for the rising concern about routing convergence as the prevalence of Internet-based real time applications. Based on the observation that highly active prefixes usually repeatedly explore very few as-paths during path exploration, we propose a router-level mechanism, Path Exploration Aggregation (PEA), to scale BGP without either causing prefix unreachable or slowing routing convergence. PEA performs aggregation on the transient paths explored by a highly active prefix, and propagates the aggregated path instead to reduce the updates caused by as-path changes. Moreover, in order to avoid the use of unstable routes, PEA purposely prolongs the aggregated path via as-path prepending to make it less preferred in the perspective of downstream routers. With the BGP traces obtained from RouteViews and RIPE-RIS projects, PEA can reduce BGP updates by up to 63.1%, shorten path exploration duration by up to 53.3%, and accelerate the convergence 7.39 seconds on average per routing event.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.75-76
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• 2006

In this paper, the polycrystalline silicon photodiodes utilizing vertically directed current path are investigated. The location of electrodes is considered with the grain direction and the current path. The relationships between grain boundaries and characteristics of photodiode are simulated to apply the vertically grown polycrystalline silicon to photodiodes. From the results, the vertically grown polycrystalline silicon photodiode is a potential candidate for CMOS image sensor. However, the increment of dark current related to grain boundaries should be reduced.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.331-332
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• 2008

A real-time path planning of mobile robots is a broad topic, covering a large spectrum of different technologies and applications. Briefly a path planning is designated moving technique from current pose to desired pose. It is remarkably easy to handle for human, not for robot. It is difficult that a robot recognizes surround to get a current pose and to avoid an obstacles. In this paper covers kinematics, path planning for efficient movements of a mobile robot. Kinematics of mobile robot which is suggested in this paper is exploited to create reliable and suitable motions. In addition, Gradient method is a algorithm which can guarantee for real-time path planning.

• 한국초전도ㆍ저온공학회논문지
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• 제6권2호
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• pp.20-24
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• 2004

Bi-2223 wire, the first-generation high temperature superconducting (HTS) wire, was successfully commercialized and various electrical machinery and equipment are actively being developed in many countries. Because its critical current is too small to realize the lossless conducting part of electric power system with a HTS wire, multi-HTS paths are used to enlarge the critical current of HTS system. Though the resistance generated in HTS wire by transport current is very small, the difference of it in multi-path is the additional reason which causes the non-uniform current sharing in multi-HTS path except the well known reason, the difference of inductance between each path. In this paper, experimental research on current sharing of multi-strand and multi-stacked HTS wire was implemented. The whole critical current of multi-HTS paths is not equal to sum of critical current of each path because of non-uniform current sharing occurred in this paths. It was verified experimentally that Bi-2223 wires have different resistance generated by same transport current even if they was manufactured in same progress of work. Current sharing phenomenon was affected by difference of resistance and self and mutual inductance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1403-1405
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• 2004

The method proposed by Carson contains indefinite complex integral which simulates earth return current. Although the Carson solution is proposed with power series, the solution is limited and valid at special range of frequency. We proposed a simplified Carson solution by modelling earth current path analytical method using ground transmission line return current. In this paper, we studied on trying to find the equivalent distance for earth current return path.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.157-161
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• 1996

In the geometric accuracy, most of studies have been concentrated on the analysis of the geometric error, or a control path of grinding using the value of measured geometric error. In this paper, by using the value of measured motor current through hall sensor, detection of the geometric error have been accomplished, and in-process control path of grinding for improvement geometric accuracy, too.

• 한국가시화정보학회지
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• 제19권2호
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• pp.56-62
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• 2021

Solid oxide fuel cells (SOFCs) is the high efficiency fuel cell operating at high temperatures ranging from 700-1000℃. Design of the flow paths of the fuel and air in SOFCs is important to improve cell performance and prevent cell degradation. However, the uneven distribution of current density in the traditional type having one inlet and outlet causes cell degradation. In this regard, the parallel flow path with two inlet and outlets was designed and compared to the traditional type based on computational fluid dynamics (CFD) simulation. To check the cell performance, hydrogen distribution, velocity distribution and current density distribution were monitored. The results validated that the parallel designs with two inlets and outlets have a higher cell performance compared to the traditional design with one inlet and outlet due to a larger reaction area. In case of uniform-type paths, more uniform current density distribution was observed with less cross-sectional variation in flow paths. In case of contracted and expanded inflow paths, significant improvement of performance and uniform current density was not observed compared to uniform parallel path. Considering SOFC cell with uniform current density can prevent cell degradation, more suitable design of SOFC cell with less cross-sectional variation in the flow path should be developed. This work can be helpful to understand the role of flow distribution in the SOFC performance.

• 전자공학회논문지C
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• 제34C권11호
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.