• Journal of Welding and Joining
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• v.16 no.6
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• pp.77-85
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• 1998

Effects of non-cleaning and cleaning fluxes on the wetting properties and defects at flow soldered joints were investigated. Non-cleaning flux (R-type of 3.3% solid content) and cleaning flux (RMA-type of 15% solid content) were used. Wetting test was accomplished by wetting balance method with changing surface state of wetting specimen, CU. Sn-37%Pb solder was used for wetting test and flow soldering. As experimental results, the wetting time for vertical force from the surface tension being zero was mainly affected by surface state of the wetting specimen. Non-cleaning flux had a good wettability compared with cleaning flux. In case of non-cleaning flux, conveyor speed had a great affection to defects of bridge, icicle, and poor solder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.76-77
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• 2005

Single crystal $CuAlSe_2$ layers were grown on thoroughly etched semi-insulating GaAs(100) substrate at 410$^{\circ}C$ with hot wall epitaxy (HWE) system by evaporating $CuAlSe_2$ source at $680^{\circ}C$. The crystalline structure of the single crystal thin films was investigated by the photoluminescence(PL) and double crystal X-ray diffraction (DCXO). The temperature dependence of the energy band gap of the $CuAlSe_2$ obtained from the absorpt ion spectra was wel1 described by the Varshni's relation, $E_g$(T) = 2.8382 eV - ($8.86\times10^{-4}$ eV/H)$T_2$/(T + 155K). After the as-grown single crystal $CuAlSe_2$ thin films were annealed in Cu-, Se-, and Al-atmospheres, the origin of point defects of single crystal $CuAlSe_2$ thin films has been investigated by PL at 10 K. The native defects of $V_{cd}$, $V_{se}$, $Cd_{int}$, and $Se_{int}$ obtained by PL measurements were classified as donors or acceptors. And we concluded that the heat-treatment in the Cu-atmosphere converted single crystal $CuAlSe_2$ thin films to an optical n-type. Also. we confirmed that hi in $CuAlSe_2$/GaAs did not form the native defects because Al in single crystal $CuAlSe_2$ thin films existed in the form of stable bonds.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Applied Microscopy
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• v.16 no.2
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• pp.14-24
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• 1986

The interrelation of secondary defects, intermediate S' phase and aging condition in Al-2.0 wt% Cu-1.1 wt% Mg alloy is studied by transmission electron microscope. The results obtained in this study are as follows. 1. High density of dislocation loops, helices and stacking faults are observed in this specimen with aging treatment. 2. The number of dislocation loops and the width of loop free zone (LFZ) are increased with aging time. 3. The intermediate S' phase precipitates and grows on the dislocations and secondary defects. 4. The misfit dislocations are formed around intermediate S' phase. 5. It is thought that the helices appear to be produced by the climb of screw dislocations, while the dislocation loops appear to be formed both by condensation of vacancies into collapsed discs and by interaction of helices with screw of opposite sign.

• Journal of the Korean Ceramic Society
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• v.37 no.8
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• pp.799-804
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• 2000

Coulometric titration experiments have been done for copper doped cobaltous oxide (Co1-xCux)1-$\delta$ O with various dopant concentrations. We present the obtained experimental data and compare our results to those of previous thermogravimetric investigation. The experimental data are fitted by theoretical calculations based on various defect models. For this modeling, we considered different types fo major defects like copper in substitutional and interstitial lattice sites as well as copper vacancy. We also introduced the copper evaporation effect during titration experiment into our consideration.

• Journal of the Korean Magnetics Society
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• v.12 no.1
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• pp.24-29
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• 2002

It was observed that exchange bias field was increased with smooth surface and better ${\gamma}$-FeMn formation. Sputtering conditions were varied for the control of the surface roughness and ${\gamma}$-FeMn formation. From the results of Cu deposition as underlayer, it was found that ${\gamma}$-FeMn formation was closely related with the thickness of underlayer. After heat treatment, exchange bias field was increased over three times. This improvement was likely that the crystallites of ${\gamma}$-FeMn were well formed. In Co/Cu/Co/FeMn spin valve structure, magnetoresistance was increased over 1.4 times through the heat treatment. This was due to the disappearance of Co/Cu intermixed dead layer and removal of defect, and this was examined by AES analysis.

• Journal of Welding and Joining
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• v.12 no.4
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• pp.85-101
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• 1994

Effect of Cr, Cu and Ni metal powders addition on the alloyed layer of aluminum alloy (AC2B) has been investigated with the plasma transferred arc (PTA) overlaying process. The overlaying conditions were 125-200A in plasma arc current, 150mm/min in process speed and 5-20g/min in powder feeding rate. Main results obtained are summarized as follows: 1) It was made clear that formation of thick surface alloyed layer on aluminum alloy is possible by PTA overlaying process. 2) The range of optimum alloying conditions were much wider in case of Cu and Ni powder additions than the case of Cr powder addition judging from the surface appearance and the bead macrostructure. 3) Alloyed layer with Cu showed almost the homogeneous microstructure through the whole layer by eutectic reaction. alloyed layers with Cr and Ni showed needle-like and agglomerated microstructures, the structure of which has compound layer in upper zone of bead by peritectic and eutectic-peritectic reactions, respectively. 4) Microconstituents of the alloyed layer were analyzed as A1+CrA $l_{7}$ eutectics, C $r_{2}$al sub 11/, CrA $l_{4}$, C $r_{4}$A $l_{9}$ and C $r_{5}$A $l_{*}$ 8/ for Cr addition, Al+CuA $l_{2}$(.theta.) eutectics and .theta. for Cu addition, and Al+NiA $l_{3}$ eutectics. NiA $l_{3}$, N $i_{2}$A $l_{3}$ and NiAl for Ni addition. 5) Concerning defect of the alloyed layer, many blow holes were seen in Cr and Ni additions although there was lesser in Cu addition. Residual gas contents in blow hole for Cu and Ni alloyed layer were confirmed as mainly $H_{2}$ and a littie of $N_{2}$ Cracking was observed in compound zone of the alloyed layer in case of Cr and Ni addition but not in Cu alloyed layer.r.r.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.47.1-47.1
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• 2011

We report on a direct measurement of two-dimensional chemical and electrical distribution on the surface of photovoltaic Cu(In,Ga)$Se_2$ thin-films using a nano-scale spectroscopic and electrical characterization, respectively. The Raman measurement reveals non-uniformed surface phonon vibration which comes from different compositional distribution and defects in the nature of polycrystalline thin-films. On the other hand, potential analysis by scanning Kelvin probe force microscopy shows a higher surface potential or a small work function on grain boundaries of the thin-films than on the grain surfaces. This demonstrates the grain boundary is positively charged and local built-in potential exist on grain boundary, which improve electron-hole separation on grain boundary. Local electrical transport measurements with scanning probe microscopy on the thin-films indicates that as external bias is increases, local current is started to flow from grain boundary and saturated over 0.3 V external bias. This accounts for carrier behavior in the vicinity of grain boundary with regard to defect states. We suggest that electron-hole separation at the grain boundary as well as chemical and electrical distribution of polycrystalline Cu(In,Ga)$Se_2$ thin-films.

• Journal of the Korean Ceramic Society
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• v.32 no.3
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• pp.313-320
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• 1995

We investigated the preferred orientation, electrical and magnetic properties of the Mn-Zn ferrite thin films deposited on SiO2/Si(100) by ion beam sputtering. The Cu-added Mn-Zn ferrite thin films had a preferred orientation of (111) with a weak orientation, (311). While the Zn-added one had a strong (111) preferred orientation. The saturation magnetization of the Cu- or Zn-doped Mn-Zn ferrite films increased with increasing substrate temperature (Ts) due to the increase of grain size and the enhancement of crystallinity. For the same reason the coercivity of Cu- or Zn-doped Mn-Zn ferrite films deposited at low Ts increased with increasing Ts, but those of the films deposited at high Ts slightly decreased not only because the defect density of the films decreases but because more grains have multi-domains with increasing Ts. The resistivity of Cu- or Zn-added Mn-Zn ferrite thin fims measured by complex impedance method decreased with increasing Ts due to the ehhancement of crystallinity as well as due to the increase of grain size.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.