• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.249-249
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• 2010

We investigated novel surface treatment and its impact on silicon photovoltaic cells. Using 2-step etching methods, we have changed the nanostructure on pyramid surface so that less light is reflected. This work proposes an improved texturing technique of mono crystalline silicon surface for solar cells with sub-nanotexturing process. The nanotextured silicon surface exhibits a lower average reflectivity (~4%) in the wavelength range of 300-1100nm without antireflection coating layer. It is worth mentioning that the surface of pyramids may also affect the surface reflectance and carrier lifetime. In one word, we believe nanotextruing is a promising guide for texturization of monocrystalline silicon surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.152-153
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• 2006

본 연구에서는 태양전지 표면에 입사된 광자의 반사손실을 최소화하기 위한 방법으로써 기판 표면에 다공성 실리콘층을 이용한 반사방지막 (Anti-Reflection Coating, ARC)을 형성하는 실험을 하였다. 다공성 실리콘(Porous silicon, PSi)은 실온에서 일정 비율로 만든 전해질 용액($HF-C_2H_5OH-H_2O$)을 사용하여 실리콘 표면을 양극산화처리 함으로써 단순 공정만으로 실리콘 기판의 반사율을 높일 수 있다. 또한 새로운 레이어(layer)없이 기존 기판을 식각시켜 만들기 때문에 박막형 태양전지를 제작시 적용이 용이하다. 저비용, 단순공정의 이점을 살려 전류밀도에 따른 PSi의 반사방지막으로써의 특성을 비교 분석하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1034-1037
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• 2003

Microcrystalline silicon(c-Si:H) thin-film solar cells are prepared with intrinsic Si-layer by hot wire CVD. The operating parameters of solar cells are strongly affected by the filament temperature ($T_f$) during intrinsic layer. Jsc and efficiency abruptly decreases with elevated $T_f$ to $1400^{\circ}C$. This deterioration of solar cell parameters are resulted from increase of crystalline volume fraction and corresponding defect density at high $T_f$. The heater temperature ($T_h$) are also critical parameter that controls device operations. Solar cells prepared at low $T_h$ ($<200^{\circ}C$) shows a similar operating properties with devices prepared at high $T_f$, i.e. low Jsc, Voc and efficiency. The origins for this result, however, are different with that of inferior device performances at high $T_f$. In addition the phase transition of the silicon films occurs at different silane concentration (SC) by varying filament temperature, by which highest efficiency with SC varies with $T_f$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.260-260
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• 2009

In high-efficiency crystalline silicon solar cell, If high-efficiency solar cells are to be commercialized, It is need to develop superior contact formation method and material that can be inexpensive and simple without degradation of the solar cells ability. For reason of plated metallic contact is not only high metallic purity but also inexpensive manufacture. It is available to apply mass production. Especially, Nickel, Copper are applied widely in various electronic manufactures as easily formation is available by plating. Ni is shown to be a suitable barrier to Cu diffusin as well as desirable contact metal to silicon. Nickel monosilicide has been suggested as a suitable silicide due to its lower resistivitym lower sintering temperature and lower layer stress than $TiSi_2$. In this paper, Nickel as a seed layer and diffusion barrier is plated by electroless plating to make nickel monosilicide.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.41.2-41.2
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• 2010

최근 태양전지 제조비용 절감을 위해 초박형 실리콘 태양전지 개발이 활발히 이루어지고 있다. 이에 따라 후면전계(Back Surface Field, BSF) 특성에 대한 관심이 높아지는 추세이다. 이에 본 연구에서는 후면의 결정방향 및 표면구조에 따라 형성되는 후면전계(BSF)의 특성에 대해 알아보고자 하였다. 후면이 절삭손상층 식각(Saw damage etching) 후 (100)면이 드러난 실리콘 기판과 텍스쳐링(Texturing) 후 (111)면이 드러난 실리콘 기판에 후면 전극을 스크린 인쇄 후 Ramp up rate을 달리 하여 소성 공정(RTP system)을 통해 후면전계(BSF)를 형성하여 비교하였다. 후면전계(BSF)의 형상과 특성만을 평가하기 위하여 염산을 이용하여 후면 전극층을 제거하였다. 후면 전극 제거 후 주사전자현미경(Scanning Electron Microscopy)과 3차원 미세형상측정기(Non-contacting optical profiler)로 후면전계(BSF)의 형상을 비교하였다. 또한 후면전계(BSF)의 특성을 평가하고자 Quasi-Steady-State Photo Conductance(QSSPC)를 사용하여 포화전류(Saturation current, $J_0$)을 측정하였고, 면저항 측정기(4-point probe)로 면저항을 측정하여 비교하였다. 후면 전계(BSF)는 (100)면과 (111)면에서 모두 Ramp up rate이 빠를수록 향상된 특성을 보였고, (111)면에서 더 큰 차이를 보였다.

• Current Photovoltaic Research
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• v.6 no.2
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• pp.49-55
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• 2018

Recently solar cell industry needs the optimal design of Czochralski process for low cost high quality silicon mono crystalline ingot. Because market needs both high efficient solar cell and similar cost with multi-crystalline Si ingot. For cost reduction in Czochralski process, first of all energy reduction should be completed because Czochralski process is high energy consumption process. For this purpose we studied optimal water-cooling tube design and simultaneously we also check the quality of ingot with Von mises stress and V(pull speed of ingot)/G(temperature gradient to the crystallization) values. At this research we used $CG-Sim^{(R)}$ S/W package and finally we got improved water-cooling tube design than normally used process in present industry. The optimal water-cooling tube length should be 200mm. The result will be adopted at real industry.

• Coupled systems mechanics
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• v.5 no.4
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• pp.341-353
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• 2016

Manufactures of multi-crystalline silicon ingots by means of the directional solidification system (DSS) is important to the solar photovoltaic (PV) cell industry. The quality of the ingots, including the grain size and morphology, is highly related to the shape of the crystal-melt interface during the crystal growth process. We performed numerical simulations to analyze the thermo-fluid field and the shape of the crystal-melt interface both for steady conditions and transient processes. The steady simulations are first validated and then applied to improve the hot zone design in the furnace. The numerical results reveal that, an additional guiding plate weakens the strength of vortex and improves the desired profile of the crystal-melt interface. Based on the steady solutions at an early stage, detailed transient processes of crystal growth can be simulated. Accuracy of the results is supported by comparing the evolutions of crystal heights with the experimental measurements. The excellent agreements demonstrate the applicability of the present numerical methods in simulating a practical and complex system of directional solidification system.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.313.1-313.1
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• 2013

현재 결정질 실리콘 태양전지의 전 후면 전극의 형성은 스크린 프린팅 방법이 주를 이루고 있다. 스크린 프린팅 방법은 쉽고 빠르게 인쇄가 가능한 반면 단가가 높고 금속 페이스트에 첨가된 여러 혼합물에 의해서 전극과 기판 사이의 저항이 크다는 단점이 있다. 본 논문에서는 스크린 프린팅 방법으로 태양전지의 seed layer를 인쇄하고, Cu도금을 진행함으로써 태양전지의 전기적 특성을 비교하였다. 주요 전극 형성을 Cu 도금을 사용함으로써 전극과 기판사이의 저항을 감소시키고 값비싼 Ag페이스트를 값싼 Cu로 대체함으로써 가격을 낮출 수 있는 장점이 있다. 실험에 사용된 Si 웨이퍼 특성은 $156{\times}156$ mm2, 200 ${\mu}m$, 0.5-3.0 ${\Omega}{\cdot}cm$ and p-type 웨이퍼를 사용하였다. 웨이퍼는 표면조직화, p-n접합 형성, 반사방지막 코팅을 하였으며 스크린 프린팅 방법을 이용해 전 후면 전극을 인쇄하고 열처리 과정을 통해 전극을 형성하였다. 이 후 전면에 Cu도금을 실행하여 태양전지를 완성하였다. 완성된 태양전지는 솔라 시뮬레이터 및 TLM패턴을 이용하여 전기적 특성을 분석하였으며, SEM과 linescan, 광학현미경 등을 이용하여 전극을 분석하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.318-321
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• 2002

This paper presents a proper condition to achieve high conversion efficiency using PC1D simulator on sri-crystalline Si solar cells. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 $\mu\textrm{m}$, front surface recombination velocity 100 cm/s, sheet resistivity of emitter layer 100 Ω/$\square$, BSF thickness 5 $\mu\textrm{m}$, doping concentration 5${\times}$10$\^$19/ cm$\^$-3/. Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %.