• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.

• Current Photovoltaic Research
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• v.1 no.1
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• pp.17-26
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• 2013

In contrast to conventional crystalline cells, back-contact solar cells feature high efficiencies, simpler module assembly, and better aesthetics. The highest commercialized cell and module efficiency was recorded by n-type back-contact solar cells. However, the mainstream PV industry uses a p-type substrate instead of n-type due to the high costs and complexity of the manufacturing processes in the case of the latter. P-type back-contact solar cells such as metal wrap-through and emitter wrap-through, which are inexpensive and compatible with the current PV industry, have consequently been developed. In this paper the characteristics of EWT (emitter wrap-through) solar cells and their status and prospects for development are discussed.

• New & Renewable Energy
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• v.4 no.2
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• pp.74-80
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.390-393
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• Korean Journal of Materials Research
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• v.26 no.8
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• pp.422-426
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• 2016

With the increase in installed solar energy capacity, comparison and analysis of the physical property values of solar cells are becoming increasingly important for production. Therefore, research on determining the physical characteristic values of solar cells is being actively pursued. In this study, a diode equation, which is commonly used to describe the I-V behavior and determine the electrical characteristic values of solar cells, was applied. Using this method, it is possible to determine the diode ideality factor (n) and series resistance ($R_s$) based on light I-V measurements. Thus, using a commercial screen-printed solar cell and an interdigitated back-contact solar cell, we determined the ideality factor (n) and series resistance ($R_s$) with a modified diode equation method for the light I-V curves. We also used the sun-shade method to determine the ideality factor (n) and series resistance ($R_s$) of the samples. The values determined using the two methods were similar. However, given the error in the sun-shade method, the diode equation is considered more useful than the sun-shade method for analyzing the electrical characteristics because it determines the ideality factor (n) and series resistance ($R_s$) based on the light I-V curves.

• Journal of the Korean Solar Energy Society
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• v.40 no.5
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• pp.35-45
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• 2020

Photovoltaic (PV) power system prices have been steadily dropping in recent years due to their mass production and advances in relevant technology. Crystalline silicon (c-Si wafers) account for the largest share of the price of solar cells; reducing the thickness of these wafers is an essential part of increasing the price competitiveness of PV power systems. However, reducing the thickness of c-Si wafers is challenging; typically, phenomena such as bowing and cracking are encountered. While several approaches to address the bowing phenomenon of the c-Si solar cells exist, the only method to study the crack phenomenon (related to the strength of the c-Si solar cells) is the bending test method. Moreover, studies on determining the strength properties of the solar cells have focused largely on c-Si wafers, while those on the strength properties of front and rear-side electrodes and SiNx, the other components of c-Si solar cells, are scarce. In this study, we analyzed the strength characteristics of each layer of c-Si solar cells. The strength characteristics of the sawing mark direction produced during the production of c-Si wafers were also tested. Experiments were conducted using a 4bending tester for a specially manufactured c-Si solar cell. The results indicate that the back side electrode is the main component that experienced bowing, while the front electrode was the primary component regulating the strength of the c-Si solar cell.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.9
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• pp.823-828
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• 2013

To reduce the cost per watt of photovoltaic power, it is important to reduce the cell thickness of crystalline silicon solar cells. As the thickness of the silicon layer is reduced, two distinctive thermal expansion rates between the silicon and the aluminum layer induce bowing in a solar cell. With a thinner silicon layer, the bowing distance grows exponentially. Excessive bowing could damage the silicon wafer. In this study, we tried to measure an irregularly curved silicon solar cell more accurately using a 3D image scanner. For the detailed analysis of the three-dimensional bowing shape, a least square fit was applied to the point data from the scanned image. It has been found that the bowing distance and shape distortion increase with a decrease in the thickness of the silicon layer. An Ag strip on top of the silicon layer can reduce the bowing distance.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.286-286
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• 2011

최근 폴리머를 기판으로 하는 Flexible TFT (thin film transistor)나 3D-ULSI (three dimensional ultra large-scale integrated circuit)에서 높은 에너지 소비효율과, 빠른 반응 속도를 실현 시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)를 가지는 다결정 반도체 박막(poly-crystalline thin film)을 만들고자 하고 있다. 이를 실현 시키기 위해서는 높은 온도에서 장시간의 열처리가 필요하며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮춰주는 metal (Al, Ni, Co, Cu, Ag, Pd etc.,)을 이용하여 결정화 시키는 방법이 많이 연구 되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔여 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도를 감소시키는 단점이 있다. 이에 본 실험은 HiPIMS (High power impulse magnetron sputtering)와 PIII and D (plasma immersion ion implantation and deposition) 공정을 복합시킨 프로세스로 적은양의 금속이온주입을 통하여 재결정화 온도를 낮췄을 뿐 아니라, 잔여 하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GAXRD (glancing angle X-ray diffractometer)를 사용하였고, 잔여 하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS를 통해 분석을 하였다. 마지막으로 홀 속도와 비저항을 측정하기 위해 Hall measurement와 Four-point prove를 사용하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.73-79
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• 2013

Crystalline silicon solar cells with $SiN_x/SiN_x$ and $SiN_x/SiO_x$ double layer anti-reflection coatings(ARC) were studied in this paper. Optimizing passivation effect and optical properties of $SiN_x$ and $SiO_x$ layer deposited by PECVD was performed prior to double layer application. When the refractive index (n) of silicon nitride was varied in range of 1.9~2.3, silicon wafer deposited with silicon nitride layer of 80 nm thickness and n= 2.2 showed the effective lifetime of $1,370{\mu}m$. Silicon nitride with n= 1.9 had the smallest extinction coefficient among these conditions. Silicon oxide layer with 110 nm thickness and n= 1.46 showed the extinction coefficient spectrum near to zero in the 300~1,100 nm region, similar to silicon nitride with n= 1.9. Thus silicon nitride with n= 1.9 and silicon oxide with n= 1.46 would be proper as the upper ARC layer with low extinction coefficient, and silicon nitride with n=2.2 as the lower layer with good passivation effect. As a result, the double layer AR coated silicon wafer showed lower surface reflection and so more light absorption, compared with $SiN_x$ single layer. With the completed solar cell with $SiN_x/SiN_x$ of n= 2.2/1.9 and $SiN_x/SiO_x$ of n= 2.2/1.46, the electrical characteristics was improved as ${\Delta}V_{oc}$= 3.7 mV, ${\Delta}_{sc}=0.11mA/cm^2$ and ${\Delta}V_{oc}$=5.2 mV, ${\Delta}J_{sc}=0.23mA/cm^2$, respectively. It led to the efficiency improvement as 0.1% and 0.23%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.260-260
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• 2009

In high-efficiency crystalline silicon solar cell, If high-efficiency solar cells are to be commercialized, It is need to develop superior contact formation method and material that can be inexpensive and simple without degradation of the solar cells ability. For reason of plated metallic contact is not only high metallic purity but also inexpensive manufacture. It is available to apply mass production. Especially, Nickel, Copper are applied widely in various electronic manufactures as easily formation is available by plating. Ni is shown to be a suitable barrier to Cu diffusin as well as desirable contact metal to silicon. Nickel monosilicide has been suggested as a suitable silicide due to its lower resistivitym lower sintering temperature and lower layer stress than $TiSi_2$. In this paper, Nickel as a seed layer and diffusion barrier is plated by electroless plating to make nickel monosilicide.