• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.811-813
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• 2003

DRM 유통 시스템 하에서 암호화된 컨텐츠의 데이터는 신뢰할 수 없는 사용자 환경에서 복호화된 이후에 사용자에게 컨텐츠에 대한 서비스를 제공하게 된다. 이러한 신뢰할 수 없는 사용자 환경에서 컨텐츠데이터를 안전하게 관리하기 위해서는 암호화 키나 라이센스 데이터등과 같은 데이터를 사용자 환경에 안전하게 보관해야 하며 이렇게 보관된 데이터는 사용자에게 꼰대 노출되지 않도록 보호를 해야 한다. 본 연구에서는 이러한 신뢰할 수 없는 사용자 환경에서 앙호화 키나 라이센스 데이터를 안전하게 보관할 수 있는 Secure Storage Device를 개발하여 소개한다.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.177-185
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• 2000

In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

• Convergence Security Journal
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• v.21 no.1
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• pp.3-7
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• 2021

In quantum cryptographic communication based on quantum mechanics, each piece of information is loaded onto individual photons and transmitted. Therefore, it is impossible to eavesdrop on only a part, and even if an intruder illegally intercepts a photon and retransmits it to the recipient, it is impossible to send the same information to the photon by the principle of quantum duplication impossible. With the explosive increase of various network-based services, the security of the service is required to be guaranteed, and the establishment of a quantum cryptographic communication network and related services are being promoted in various forms. However, apart from the development of Quantum Key Distribution (QKD) technology, a lot of research is needed on how to provide network-level services using this. In this paper, based on the quantum encryption device, we propose an integrated data structure for transferring quantum keys between various quantum encryption communication network devices and realizing an encrypted transmission environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1283-1288
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• 2015

In general, IC chip circuit which is operating a cryptographic computation tends to radiate stronger electromagnetic signal to the outside. By using a power detecter such as a loop antenna near cryptographic device, the encryption key can be identified by probing a electromagnetic signal. To implement a method against non-invasive type attack, multi dielectric slab structure on IC chip to suppress radiated electromagnetic signal was introduced. Multiple dielectric slab was implemented by suitably configured to have the Bragg reflection characteristics, and then the reflection response was computed and verified its effectiveness. As a result, the thickness of the dielectric coating was 2mm and the reflection response characteristics for the vertical incidence was achieved to be 91% level.

• Journal of Korea Multimedia Society
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• v.20 no.12
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• pp.1913-1927
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• 2017

Encryption technology is to hide information in a cyberspace built using a computer and to prevent third parties from changing it. If a malicious user accesses unauthorized device or application services on the Internet of objects, it may be exposed to various security threats such as data leakage, denial of service, and privacy violation. One way to deal with these security threats is to encrypt and deliver the data generated by a user. Encrypting data must be referred to a technique of changing data using a complicated algorithm so that no one else knows the content except for those with special knowledge. As computers process computations that can be done at a very high speed, current cryptographic techniques are vulnerable to future computer performance improvements. We designed and implemented a new encryption program that combines ancient and modern cryptography so that the user never knows about data management, and transmission. The significance of this paper is that it is the safest method to combine various kinds of encryption methods to secure the weaknesses of the used cryptographic algorithms.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.415-420
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• 2010

Cryptographic keys for security should be generated by true random number generators that apply irreversible hashing algorithms to initial values taken from a random source. As DRAM shows randomness in its access latency, it can be used as a random source. However, systems with synchronous DRAM (SDRAM) do not easily expose such randomness resulting in highly clustered random numbers. We resolved this problem by using the xor instruction. Statistical testing shows that the generated random bits have the quality comparable to true random bit sequences. The performance of bit generation is at the order of 100 Kbits/sec. Since the proposed random number generation requires neither external devices nor any special circuits, this method may be used in any computing device that employs DRAM.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.264-271
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• 2021

From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2C
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• pp.208-218
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• 2008

We are sure that RFID system should be a widely used automatic identification system because of its various advantages and applications. However, many people know that invasions of privacy in RFID system is still critical problem that makes it difficult to be used. Many works for solving this problem have focused on light-weight cryptographic functioning in the RFID tag. An agent scheme is another approach that an agent device controls communications between the tag and the reader for protecting privacy. Generally an agent device has strong security modules and enough capability to process high-level cryptographic protocols and can guarantees consumer privacy. In this paper, we present an enhanced mobile agent for RFID privacy protection. In enhanced MARP, we modified some phases of the original MARP to reduce the probability of successful eavesdropping and to reduce the number of tag's protocol participation. And back-end server can authenticate mobile agents more easily using public key cryptography in this scheme. It guarantees not only privacy protection but also preventing forgery.