• Journal of Information Processing Systems
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• v.5 no.4
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.95-105
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• 2002

This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.879-882
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• 2003

Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.8-15
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• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.157-162
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• 2010

Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1399-1402
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• 2003

Paul Hocker has developed new attacks based on the electric consumption of cryptographic device such as smartcard that performs cryptographic computation. Among those attacks, the Differential Power Analysis(DPA) is one of the most impressive and most difficult to avoid. By analysing the power dissipation of encryption in a device, the secret information inside can be deduced. This paper presents that Advanced Encryption Standard(AES) is highly vulnerable to DPA and readily leaks away all secret keys through the experimental results for DPA. After all, it is required an implementation of the AES algorithm that is not vulnerable to DPA. We also propose countermeasures that employ asynchronous circuit.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.269-271
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• 2005

EMV was formed in February 1999 by Europay International, MasterCard International and Visa International to manage, maintain and enhance the EMV Integrated Circuit Card Specifications for Payment Systems as technology advances and the implementation of chip card programs become more prevalent. The formation of EMV ensures that single terminal and card approval processes are developed at a level that will allow cross payment system interoperability through compliance with the EMV specifications. A credit card environment of the domestic market adopted the standard Local-EMV to have the compatibility with EMV international standard and the EMV migration have been carried out b,# the step-by-step process. It may be possible to adopt various kinds of cryptographic algorithms, however, RSA public key algorithm is currently used. In this paper, as a public key algorithm for the authentication process, Elliptic Curve Cryptographic algorithm is applied to the EMV process. Implementation results is shown. and the possible changes necessary to accommodate Elliptic Curve Cryrtography is proposed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.323-330
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• 2021

Recently, the advantages of high-speed arithmetic in quantum computers have been known, and interest in quantum circuits utilizing qubits has increased. The Grover algorithm is a quantum algorithm that can reduce n-bit security level symmetric key cryptography and hash functions to n/2-bit security level. Since the Grover algorithm work on quantum computers, the symmetric cryptographic technique and hash function to be applied must be implemented in a quantum circuit. This is the motivation for these studies, and recently, research on implementing symmetric cryptographic technique and hash functions in quantum circuits has been actively conducted. However, at present, in a situation where the number of qubits is limited, we are interested in implementing with the minimum number of qubits and aim for efficient implementation. In this paper, the domestic hash function LSH is efficiently implemented using qubits recycling and pre-computation. Also, major operations such as Mix and Final were efficiently implemented as quantum circuits using ProjectQ, a quantum programming tool provided by IBM, and the quantum resources required for this were evaluated.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.940-943
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• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.