• Title/Summary/Keyword: Critical path tracing

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A Study of Efficiency Improvement of the D-algorithm for NAND Circuits (NAND회로망의 시험패턴발생을 위한 D-알고리듬의 효율개선에 관한 연구)

  • 노정호;강병욱;안광선
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.7
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    • pp.734-745
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    • 1988
  • In this paper, it is tried to improve efficiency of the D-algorithm by assigning the logic values effectively on the nodes related to the critical path for back tracing to reduce the number of search nodes when acyclic combinational logic circuits are composed of NAND gates only. For that purpose, LASAR algorithm which is suitable for determining a critical path for back tracing is applied to the D-algorithm and it is implemented by IBM-PC with APL language. The test results on a number of NAND circuits which have multi-fanout, reconvergent and symetric characteristics show that the modified D-algorihtm reduces the number of search nodes in forward and backward tracing and decreases the run time of CPU about 10 percents.

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A Pattern Comparison Algorithm for Pruning Fault Candidates (고장 대상 후보를 줄이기 위한 패턴 비교 알고리즘)

  • Cho, Hyung-Jun;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.82-88
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    • 2007
  • In this paper, we present a pattern comparison algorithm for reducing fault candidate lists. The number of fault candidates determines the total fault simulation time. To decrease the total fault diagnosis time, the reduction of the number of fault candidates is essential. Critical path tracing determines fault candidate lists detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. The proposed algorithm reduces fault candidates comparing failing patterns with good patterns during critical path tracing process. As we reduce all fault candidates of the circuit to more accurately suspected fault candidates, we can greatly reduce fault simulation time. The proposed algorithm greatly increases simulation speed than that of a conventional backtracing method. The proposed algorithm is applicable to both combinational and sequential circuits. Experimental results on ISCAS#85 and ISCAS#89 benchmark circuits showed fault candidates are pruned and fault diagnosis time is also decreased in proportion to fault candidate decrease.

Implementation of Ray Tracing Processor for the Parallel Processing (병렬처리를 위한 고속 Ray Tracing 프로세서의 설계)

  • Choe, Gyu-Yeol;Jeong, Deok-Jin
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.5
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    • pp.636-642
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    • 1999
  • The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

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A Study on the Geometrically Nonlinear Analysis of Spatial Structures by Using Arc Length Method (호장법을 이용한 공간구조의 기하학적 비선형 해석에 관한 연구)

  • Han, Sang-Eul;Lee, Sang-Ju;Lee, Kyoung-Soo
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 2007.04a
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    • pp.381-386
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    • 2007
  • The present study is concerned with the application of Constant arc-length method that proposed by Crisfield in the investigation of the geometrically nonlinear behaviour of spatial structures composed by truss or beam element. The arc-length method can trace the full nonlinear equilibrium path of Spatial structure far beyond the critical point such as limit or bifurcation point. So, we have developed the constant arc-length method of Crisfield to analysis spatial structure. The finite element formulation is used to develop the 3d truss/beam element including the geometrical nonlinear effect. In an effort to evaluate the merits of the methods, extensive numerical studies were carried out on a number of selected structural systems. The advantages of Constant arc length method in tracing the post-buckling behavior of spatial structures, are demonstrated.

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Improvement of Telematics Technology Utilizing Logistics Information (물류정보를 활용한 텔레매틱스 기술 개선방안)

  • Byeon, Eui-Seok
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.32 no.2
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    • pp.38-44
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    • 2009
  • Recently, automobile industry expands from mechatronics area through intelligent information area, and the telematics technology is one of the greatest developing points. The telematics is utilizing the on-board-unit of vehicle's communication system, and it provides necessary information and value-added service to vehicles as well as drivers. Most of the telematics offers the solution of searching a route or generates an optimal path. This paper investigates telematics with the logistics point of view, such as freight location tracking, vehicle emergency information, etc. The telematics is a core technology of automobile industry, and it becomes new business paradigm of IP(information provider). Especially, ETA(estimated arrival time) of freight and distribution tracing information are critical issues in the logistics industry. The successful integration with telematics is introduced in the paper.

Evaluation of Artificial Intelligence-Based Denoising Methods for Global Illumination

  • Faradounbeh, Soroor Malekmohammadi;Kim, SeongKi
    • Journal of Information Processing Systems
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    • v.17 no.4
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    • pp.737-753
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    • 2021
  • As the demand for high-quality rendering for mixed reality, videogame, and simulation has increased, global illumination has been actively researched. Monte Carlo path tracing can realize global illumination and produce photorealistic scenes that include critical effects such as color bleeding, caustics, multiple light, and shadows. If the sampling rate is insufficient, however, the rendered results have a large amount of noise. The most successful approach to eliminating or reducing Monte Carlo noise uses a feature-based filter. It exploits the scene characteristics such as a position within a world coordinate and a shading normal. In general, the techniques are based on the denoised pixel or sample and are computationally expensive. However, the main challenge for all of them is to find the appropriate weights for every feature while preserving the details of the scene. In this paper, we compare the recent algorithms for removing Monte Carlo noise in terms of their performance and quality. We also describe their advantages and disadvantages. As far as we know, this study is the first in the world to compare the artificial intelligence-based denoising methods for Monte Carlo rendering.