• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.139-145
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• 2005

In the study, in order to deposit TaN thin film using diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristic of TaN thin films deposited PAALD method, PAALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamlno) tantalum) Precursor and $NH_3$ reaction gas is aware that TaN thin film deposited of high density and amorphous phase with XRD measurement The degree of diffusion and react ion taking place in Cu/TaN(deposited using 150 W PAALD)/$SiO_2$/Si systems with increasing annealing temperature was estimated from MOS capacitor property and the $SiO_2(600\;\AA)$/Si system surface analysis by C-V measurement and secondary ion material spectrometer(SIMS) after Cu/TaN/$SiO_2(400\;\AA)$ system etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to $500^{\circ}C$.

• 반도체디스플레이기술학회지
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• 제4권2호
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• pp.39-43
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• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• 한국재료학회지
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• 제19권7호
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• pp.349-355
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• 2009

Metal thin film patterns on a LTCC substrate, which was connected through inner via and metal paste for electrical signals, were formed by a screen printing process that used electric paste, such as silver and copper, in a conventional method. This method brought about many problems, such as non uniform thickness in printing, large line spaces, and non-clearance. As a result of these problems, it was very difficult to perform fine and high resolution for high frequency signals. In this study, the electric signal patterns were formed with the sputtered metal thin films (Ti, Cu) on an LTCC substrate that was coated with protective oxide layers, such as $TiO_2$ and $SiO_2$. These electric signal patterns' morphology, surface bonding strength, and effect on electro plating were also investigated. After putting a sold ball on the sputtered metal thin films, their adhesion strength on the LTCC substrate was also evaluated. The protective oxide layers were found to play important roles in creating a strong design for electric components and integrating circuit modules in high frequency ranges.

• 자원리싸이클링
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• 제26권5호
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• pp.85-96
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• 2017

본 연구에서는 PCB 도금 및 에칭 공정 중 발생한 슬러지의 분석을 통해 건식환원처리가 가능한 슬래그 시스템을 선정하고자 하였으며 이를 바탕으로 슬러지 내에 존재하는 유가금속의 회수 가능성에 대하여 실험적 및 열역학적 검토를 하였다. 슬러지는 $100{\sim}500^{\circ}C$의 온도구간에서 건조한 후 슬러지의 형상과 화학성분 및 상을 분석하였다. 슬러지의 건식환원처리 가능성은 FactSage를 이용한 열역학적 계산을 통해 조사하였다.

• 대한금속재료학회지
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• 제48권7호
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.79-84
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• 2014

Citric acid 함유 diethylene glycol 용매 기반 용액의 치환 은도금 특성을 분석하기 위하여 Cu 박막 시편을 사용한 상온~$50^{\circ}C$ 온도 범위에서의 도금을 실시하였다. 사용된 Cu 박막 시편은 스퍼터링된 Cu를 과에칭하여 다수의 핀홀이 형성된 상태로 사용하였다. 도금을 $40^{\circ}C$에서 실시한 경우 갈바닉 치환 반응이 주로 발휘되면서 5분간의 도금 후에는 Cu 표면의 핀홀들이 완전히 Ag로 채워지고 Cu 표면도 전면적으로 Ag로 도금된 결과를 관찰할 수 있어 가장 우수한 Ag도금 특성을 얻을 수 있었다. 이후 도금 시간을 30분까지 증가시키게 되면 용액 내 환원 반응을 통한 입자들의 증착이 진행되면서 Ag 도금부의 요철이 점차 심해지는 현상이 관찰되었다. 전면적이 Ag로 도금된 Cu 시편의 대기 중 고온 내산화성을 평가한 결과 Ag가 도금되지 않은 Cu 시편에 비해 약 $50^{\circ}C$ 정도가 높은 온도에서 산화 거동이 관찰되어 향상된 내산화 특성을 확인할 수 있었다.