• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.726-728
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• 2016

In this paper, a realtime MIDI controller is designed using leap motion. The controller makes virtual MIDI port on Windows that it is connected to the port and protocol for communication with DAW or VST. It is converted MIDI data when it is detected a real time the position and shape of hand. This converted data transfer MIDI port by MIDI CC(Control Change). Therefore this controller has the purpose to support flexible MIDI input function than existed MIDI controller.

• Fire Science and Engineering
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• v.11 no.2
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• pp.35-44
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• 1997

In this paper, I present an architecture and techniques to monitor and identify the hazards of plants anywhere in the whole country using the HTTP(Hypertext Transfer Protocol) based on RFC1945 and PLC(Programmable Logic Controller) protocol. I constructed the upward network and downward network for intercommunication between the PLC and computer around the internet. I also constructed WWW(World-Wide Web) server in the personal computer The result of this research constructed monitoring system to monitor and identify the hazards through WWW browser on the internet.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1857-1863
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• 2012

The VDS(Vehicle Detection System) collects and transfers information about traffic situations in real time, therefore it makes the traffic management effective. Recently, the VDSs have provided good stability and accuracy in regard to system reliability and functions but they also have showed problems such as raising costs and consuming times when a new system is installed and/or the environmental requirements for the system are set up. The reason of the problems is that up to now the collection of the data and information about the traffic situations has been achieved by the 1:1 information exchange between the traffic control surveillance center and the each traffic field, between equipments and centers, and among data processing equipments and also centers. The communication systems used in the VDS are generally composed of 1 : 1 connection of the lines because the communication protocols are different in the most of the cases mentioned above. Consequently, this makes the number of communication lines become larger and causes the cost for the whole traffic information systems to increase. In this paper, a development of a controller to unify the communication protocols for the VDS is peformed to solve the problems which were mentioned above. Specially, the controller developed in this paper was applied to a radar vehicle detector and tested to show its usefulness. In addition to that, the developed controller was also designed to include functions to transfer the information about weather conditions on the roads.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2109-2111
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• 2003

In this paper, It is studied to monitor the remote system status using HTTP(HyperText Transfer Protocol) object communication. This system is organized by three different part depending on functionality - server part, client part, controller part. The JAVA technology is used to composite the server part, the client part and C language is used for a controller.

• Journal of Korea Multimedia Society
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• v.22 no.2
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• pp.178-185
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• 2019

Recently, due to the rapid growth of the internet the existing network architecture is showing limitations. In order to overcome these problems SDN has been proposed as a new paradigm. EIGRP is a modern routing protocol with many advantages but little research has been done on operation in SDN. In this paper we propose a controller-centric EIGRP based on the SDN environment. To construct the SDN network, We seperate the control function and the data transfer function and the EIGRP is operated by a separated controller. Experiments have shown that the proposed scheme can actually work and be used effectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.107-113
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• 2005

In this paper, Web server is built up using PXA255, 32bit RISC processor with porting Embedded Linux and GoAhead HTTP(Hyper Text Transfer Protocol) web server, and the system which can monitor and control the environment and condition for AICC(Automatic Intelligent Cruise Control) is realized For sensing the operation condition and change of vehicle the desired data is derived by interfacing ECU(Electric Control Unit) and Embedded system and the rpm of engine is controlled by step motor connected to throttle valve.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.665-668
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• 2003

In this paper, we have designed and implemented the RAID controller board which connects to the host computer with serial ATA interface and connects to the disks with parallel ATA interface. Serial ATA interface is proposed to overcome the design limitation of parallel ATA while enabling the storage interface to scale with the slowing media rate demands for PC platforms. Serial ATA is to replace parallel ATA with the compatibility with existing operating systems and drivers, adding performance headroom for years to come. It Moreover, serial ATA provides even faster transfer rate of 150 Mbytes/s which is larger than that of current parallel ATA. The RAID controller board designed in this paper combines up to 4 disks with parallel ATA interface, and connects to PC host computer with serial ATA interface. We have implemented RAID controller using Verilog HDL language with FPGA chip. The RAID controller supports RAID level 0 and 1 functionality. Experimently, the average read/write performance of parallel ATA interface is about 30 Mbytes/s. Therefore, when 4 parallel disks is connected to the RAID controller board, we can get almost full throughput of serial ATA protocol using the RAID level 0 configuration with 4 disks.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.257-260
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• 1988

A protocol on transferring informations between IBM-PC/AT and STC(self tuning controller) by using the RS-485 bus is suggested. The operating algorithm is designed so that the host computer monitors the status of STC, and can be updating parameters depending on the environmental conditions for the various oprating mode.