• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.179-184
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• 1999

A Timing Diagram is almost used to represent the various signals such as an address bus, a data bus, and the control signals during design and analysis of a digital system. But if so, its representation is somewhat complicated and also it is difficult to analyze the operation of the system. In this paper, we proposed the representation method of timing diagrams with the EMFG(Extended Mark Flow Graph). In the EMFG representation of the system operation, the logical states due to the various signals of the system is graphically represented. Therefore the proposal method allows that it is easy to design as well as analyze the system. As examples applied, we represented the memory read cycle of $\mu$PD70320 CPU and the read cycle of MCM60256A memory with the EMFG.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1975-1986
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• 1997

Recent evolution of communication networks has led toward increasingly a complex, large-scale protocol. Protocol conformance tests therefore, which consider only control flow, have many problems on testing data flow, transition condition, delay and so on. We propose, design, and implement the tool to solve these problems. The tool, which solves nondeterminism, generates test suites from an integrated flow graph and excludes infeasible path with reachable tree. The presented tool reduces the length of UIO sequence and is efficient partially to test the path that error rate is high. Our automatic test suite generator provides basis of protocol testing environment and high production.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.795-807
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• 2005

The classical approaches for computing Live Variable Analysis(LVA) use iterative algorithms across the entire programs based on the Data Flow Analysis framework. In case of Zephyr compiler, average execution time of LVA takes $7\%$ of the compilation time for the benchmark programs. The classical LVA algorithm has many aspects for improvement. The iterative algorithm for LVA scans useless basic blocks and calculates large sets of variables repeatedly. We propose the improvement of Iterative algorithm for LVA based on used variables' upward movement. Our algorithm produces the same result as the previous iterative algorithm. It is based on use-def chain. Reordering of applying the flow equation in DFA reduces the number of visiting basic blocks and redundant flow equation executions, which improves overall processing time. Experimental results say that our algorithm ran reduce $36.4\%\;of\;LVA\;execution\;time\;and\;2.6\%$ of overall computation time in Zephyr compiler with benchmark programs.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1728-1731
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• 2002

Scheduling is assigning each operation in a control/data flow graph(CDFG) to a specific control step. It directly influences the performance of the hardware synthesized. In this paper, we propose an efficient resource-constrained scheduling algorithm assuming that only available silicon area is given. We performed the experiment to evaluate its performance. The results show that our algorithm find the solution with shorter scheduling length compared to the existing methods.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.87-98
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• 2008

In company with the demand of powerful processing units for embedded systems, the method to develop embedded software is also required to support the demand in new approach. In order to improve the resource utilization and system performance, software modeling techniques have to consider the features of hardware architecture. This paper proposes a partitioning technique of UML-based software models, which focus the generation of the allocatable software components into multiprocessor architecture. Our partitioning technique, at first, transforms UML models to CBCFGs(Constraint-Based Control Flow Graphs), and then slices the CBCFGs with consideration of parallelism and data dependency. We believe that our proposition gives practical applicability in the areas of platform specific modeling and performance estimation in model-driven embedded software development.

• Proceedings of the IEEK Conference
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• summer
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• pp.259-262
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• 2004

In most of the character recognition systems, the method of template matching or statistical method using hidden Markov model is used to extract and recognize feature shapes. In this paper, we used modified chain-code which has 8-directions but 4-codes, and made the chain-code of hand-written character, after that, converted it into transition chain-code by applying to HMM(Hidden Markov Model). The transition chain code by HMM is analyzed as signal flow graph by Mason's theory which is generally used to calculate forward gain at automatic control system. If the specific forward gain and feedback gain is properly set, the forward gain of transition chain-code using Mason's theory can be distinguished depending on each object for recognition. This data of the gain is reorganized as tree structure, hence making it possible to distinguish different hand-written characters. With this method, $91\%$ recognition rate was acquired.

• The KIPS Transactions:PartD
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• v.14D no.2
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• pp.217-224
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• 2007

In order to determine the value and type statically. CTOC uses the SSA Form which separates the variable according to assignment. The SSA Form is widely being used as the intermediate expression of the compiler for data flow analysis as well as code optimization. However, the conventional SSA Form is more associated with variables rather than expressions. Accordingly, the redundant expressions are eliminated to optimize expressions of the SSA From. This paper defines the partial redundant expression to obtain a more optimized code and also implements the technique for eliminating such expressions.

• The Journal of the Korea Contents Association
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• v.6 no.2
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• pp.117-126
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• 2006

Although the Java bytecode has numerous advantages, there are also shortcomings such as slow execution speed and difficulty in analysis. In order to overcome such disadvantages, bytecode analysis and optimization must be performed. First control flow of the bytecode should be analyzed, after which information is required regarding where the variables are defined and used to conduct data flow analysis and optimization. There may be cases where variables with an identical name contain different values at a different location during the execution according to the value assigned to a variable in each location. Therefore, in order to statically determine the value and type, the variables must be separated according to allocation. In order to do so, the variables can be expressed using a static single assignment form. After the transformation into a static single assignment form, the type information of each node expressed by each variable and expression must be configured to perform static analysis and optimization. Based on the basic type information, this paper proposes a method for finding related equivalent nodes, setting the nodes with strongly connection components and efficiently assigning each node the type.