• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2016년도 추계학술대회
• /
• pp.655-658
• /
• 2016

고성능 디지털 회로 구현에 매우 많이 사용되는 Xilinx사의 7-Series FPGA(Field Programmable Gate Array)는 configuration memory가 SRAM 기반으로 제작되어 configuration memory에 소프트 에러(soft error)가 발생하는 경우 FPGA는 오동작하게 된다. Xilinx사에서 제공하는 SEM(Soft Error Mitigation) Controller를 이용하면 configuration memory에서 발생하는 소프트 에러의 영향을 줄일 수 있다. SEM Controller는 FPGA의 configuration memory 영역에 추가된 ECC(Error Correction Code)와 CRC(Cyclic Redundancy Code) 기능을 이용하여 configuration memory에 발생한 소프트 에러를 감지하여 필요시 partial reconfiguration 과정을 수행하여 FPGA의 기능을 소프트 에러 발생 이전으로 복구한다. 본 논문에서는 Xilinx사의 7-Series FPGA에서 SEM Controller를 이용하여 configuration memory의 소프트 에러를 검출하고 정정할 때 FPGA의 신뢰도를 가용성(availability) 관점에서 분석한다. 이를 위해 SEM Controller의 소프트 에러 정정 성능에 따른 가용성 함수를 유도하고 그 효과를 검토한다. 연구 결과는 소프트 에러가 발생하는 환경에서 동작하는 SRAM 기반 FPGA의 신뢰성 예측에 사용할 수 있을 것으로 기대된다.

• 한국정보통신학회논문지
• /
• 제21권3호
• /
• pp.601-606
• /
• 2017

고성능 디지털 회로 개발과 구현에 사용되는 SRAM 기반 FPGA(Field Programmable Gate Array)는 configuration memory가 SRAM으로 구현되었기 때문에 configuration memory에 소프트 에러가 발생하는 경우 오동작하게 된다. Xilinx사의 FPGA는 configuration memory 영역에 추가된 ECC(Error Correction Code)와 CRC(Cyclic Redundancy Code) 그리고 이들을 활용하는 SEM(Soft Error Mitigation) Controller를 이용하여 이러한 소프트 에러의 영향을 줄일 수 있다. 본 연구에서는 SRAM 기반 FPGA에서 SEM Controller에 의해 configuration memory 영역이 소프트 에러로부터 보호될 때 FPGA의 신뢰도를 가용성 관점에서 해석하고 그 효과를 분석하였다. 이를 위해 FPGA 계열별 SEM Controller의 소프트 에러 정정 성능에 따른 가용성 함수를 유도하고 FPGA 계열별 사례를 적용하여 비교하였다. 연구 결과는 SRAM 기반 FPGA의 선정 및 가용성 예측에 활용될 수 있을 것으로 기대된다.

• Journal of Electrical Engineering and information Science
• /
• 제2권4호
• /
• pp.8-13
• /
• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• 대한임베디드공학회논문지
• /
• 제12권4호
• /
• pp.193-204
• /
• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• 한국정밀공학회지
• /
• 제13권9호
• /
• pp.54-61
• /
• 1996

Because of its high energy density, the use of shape memory alloys(SMA) in designing microactuatiors is gaining much attention in recent years. Shape memory alloys can undergo a shape change at a low temperature with a small applied deformation force, and retain this deformation until they are heated, at which point they return to the original shape. This is called the shape memory effect(SME), and a plethora of alloys show this effect. Among them, TiNi-based alloys have relatively high electrical resistivity, which to develope helical-shape memory springs. These springs are used to develop fast protatonist/antagonist configuration actuators. The developed actuator has an actuation speed of 1 mm per 15 .approx. 20 ms and a minimum operating period of 2 sec.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제12권11호
• /
• pp.5234-5251
• /
• 2018

It is well-known that virtualization technology can bring many benefits not only to users but also to service providers. From the view of system security and resource utility, higher resource sharing degree and higher system reliability can be obtained by the introduction of virtualization technology in distributed cloud. The small size time-sharing multiplexing technology which is based on virtual machine in distributed cloud platform can enhance the resource utilization effectively by server consolidation. In this paper, the concept of memory block and user satisfaction is redefined combined with user requirements. According to the unbalanced memory resource states and user preference requirements in multi-virtual machine environments, a model of proper memory resource allocation is proposed combined with memory block and user satisfaction, and at the same time a memory optimization allocation algorithm is proposed which is based on virtual memory block, makespan and user satisfaction under the premise of an orderly physical nodes states also. In the algorithm, a memory optimal problem can be transformed into a resource workload balance problem. All the virtual machine tasks are simulated in Cloudsim platform. And the experimental results show that the problem of virtual machine memory resource allocation can be solved flexibly and efficiently.

• 한국전기전자재료학회논문지
• /
• 제35권5호
• /
• pp.452-458
• /
• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• 반도체디스플레이기술학회지
• /
• 제6권2호
• /
• pp.5-10
• /
• 2007

According to the advantageous features of flash memory, its exploitation and application in mobile and ubiquitous related devices as well as voluminous storage devices is being increased rapidly. The inherent properties that are determined by configuration of flash memory unit might restrict the promising expansion in its utilization. In this paper, we study policies based on threshold values, instead of using global search, in order to satisfy our objective that is to decrease the necessary processing cost or penalty for recycling of flash memory space at the same time minimizing the potential degradation of performance. The proposed cleaning methods create partitions of candidate memory regions, to be reclaimed as free, by utilizing global or dynamic threshold values. The impact of the proposed policies is evaluated through a number of experiments, the composition of the optimal configuration featuring the methods is tested through experiments as well.

• 전자공학회논문지C
• /
• 제35C권11호
• /
• pp.39-47
• /
• 1998

본 논문에서는 공유 버퍼 ATM 스위치를 위한 파이프라인 방식의 고속 메모리 구조를 제안하고 설계하였다. 제안된 메모리 구조는 빠른 동작 속도와 용량 가변성을 지원하여 공유 버퍼 ATM 스위치가 가지는 메모리 cycle time의 제한을 극복하였다. 본 메모리 구조가 지원하는 용량 가변성은 ATM 스위치에서의 교환 성능 가변성을 제공한다. 본 메모리 구조는 작은 메모리 bank들로 이루어진 2차원 배열 구조를 가진다. 메모리 용량은 부가적인 메모리 bank들을 추가하여 메모리 bank들의 배열 크기를 증가 시킴으로 인해 증가된다. 설계된 파이프라인 방식의 메모리는 4160 bit 메모리 bank를 16개 이용하여 4 × 4의 배열로 설계하였고 전체 용량은 65 Kbit이다. 레이아웃후 시뮬레이션을 통한 최대 동작 속도는 5 VV/sub dd/ 및 25℃에서 4ns이다. 설계된 메모리는 공유 가변 버퍼 ATM 스위치의 시험 설계된 칩에 내장되었다. 시험 설계된 칩은 0.6 ㎛ 2-metal 1-poly CMOS 공정 기술을 이용하여 설계하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.451-452
• /
• 2008

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints. Our procedure uses ILP models to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound. If we have a margin in time constraint, we break up conflict edges and expend the search space of ILP. This method effectively reduces area and power of the designed results.