• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.655-658
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• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.601-606
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• 2017

SRAM-based FPGAs mainly used to develop and implement high-performance circuits have SRAM-type configuration memory. Soft errors in memory devices are the main threat from a reliability point of view. Soft errors occurring in the configuration memory of FPGAs cause FPGAs to malfunction. SEM(Soft Error Mitigation) Controllers offered by Xilinx can mitigate the influence of soft errors in configuration memory. SEM Controllers use ECC(Error Correction Code) and CRC(Cyclic Redundancy Code) which are placed around the configuration memory to detect and correct the errors. The correction is done through a partial reconfiguration process. This paper presents the availability analysis of SRAM-based FPGAs against soft errors under the protection of SEM Controllers. Availability functions were derived and compared according to the correction capability of SEM Controllers of several different families of FPGAs. The result may help select an SRAM-based FPGA part and estimate the availability of FPGAs running in an environment where soft errors occur.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.9
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• pp.54-61
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• 1996

Because of its high energy density, the use of shape memory alloys(SMA) in designing microactuatiors is gaining much attention in recent years. Shape memory alloys can undergo a shape change at a low temperature with a small applied deformation force, and retain this deformation until they are heated, at which point they return to the original shape. This is called the shape memory effect(SME), and a plethora of alloys show this effect. Among them, TiNi-based alloys have relatively high electrical resistivity, which to develope helical-shape memory springs. These springs are used to develop fast protatonist/antagonist configuration actuators. The developed actuator has an actuation speed of 1 mm per 15 .approx. 20 ms and a minimum operating period of 2 sec.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5234-5251
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• 2018

It is well-known that virtualization technology can bring many benefits not only to users but also to service providers. From the view of system security and resource utility, higher resource sharing degree and higher system reliability can be obtained by the introduction of virtualization technology in distributed cloud. The small size time-sharing multiplexing technology which is based on virtual machine in distributed cloud platform can enhance the resource utilization effectively by server consolidation. In this paper, the concept of memory block and user satisfaction is redefined combined with user requirements. According to the unbalanced memory resource states and user preference requirements in multi-virtual machine environments, a model of proper memory resource allocation is proposed combined with memory block and user satisfaction, and at the same time a memory optimization allocation algorithm is proposed which is based on virtual memory block, makespan and user satisfaction under the premise of an orderly physical nodes states also. In the algorithm, a memory optimal problem can be transformed into a resource workload balance problem. All the virtual machine tasks are simulated in Cloudsim platform. And the experimental results show that the problem of virtual machine memory resource allocation can be solved flexibly and efficiently.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.5-10
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• 2007

According to the advantageous features of flash memory, its exploitation and application in mobile and ubiquitous related devices as well as voluminous storage devices is being increased rapidly. The inherent properties that are determined by configuration of flash memory unit might restrict the promising expansion in its utilization. In this paper, we study policies based on threshold values, instead of using global search, in order to satisfy our objective that is to decrease the necessary processing cost or penalty for recycling of flash memory space at the same time minimizing the potential degradation of performance. The proposed cleaning methods create partitions of candidate memory regions, to be reclaimed as free, by utilizing global or dynamic threshold values. The impact of the proposed policies is evaluated through a number of experiments, the composition of the optimal configuration featuring the methods is tested through experiments as well.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.451-452
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• 2008

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints. Our procedure uses ILP models to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound. If we have a margin in time constraint, we break up conflict edges and expend the search space of ILP. This method effectively reduces area and power of the designed results.