• Journal of Korea Multimedia Society
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• v.18 no.11
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• pp.1332-1341
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• 2015

This paper proposes a novel reversible secret sharing scheme using AES algorithm in encrypted images. In the proposed scheme, a role of the dealer is divided into an image provider and a data hider. The image provider encrypts the cover image with a shared secret key and sends it to the dealer. The dealer embeds the secret data into the encrypted image and transmits encrypted shadow images to the corresponding participants. We utilize Galois polynomial arithmetic operation over 2⁸ and the coefficient of the higher-order term is fixed to one in order to prevent the overflow. In experimental results, we demonstrate that the PSNR is sustained close to 44dB and the embedding capacity is 524,288 bits.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.93-98
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• 2003

This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.3
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• pp.329-337
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• 2000

This study describes a pressure tracking control of hydroforming process which is used for precision forming of sheet metals. The hydroforming operation is performed in the high-pressure chamber strictly controlled by pressure control valve and by the upward motion of a punch moving at a constant speed, The pressure tracking control is very difficult to design and often does not guarantee satisfactory performances be-cause of the punch motion and the nonlinearities and uncertainties of the hydraulic components. To account for these nonlinearities and uncertainties of the process and iterative learning controller is proposed using Cerebellar Model Arithmetic Computer (CMAC). The experimental results show that the proposed learning control is superior to any fixed gain controller in the sense that it enables the system to do the same work more effectively as the number of operation increases. In addition reardless of the uncertainties and nonlinearities of the form-ing process dynamics it can be effectively applied with little a priori knowledge abuot the process.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.81-87
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• 2013

In this paper, we present an implementation of Long Term Evolution (LTE) Uplink (UL) system on a Software Defined Radio (SDR) platform using a conventional Personal Computer (PC), which adopts Graphic Processing Units (GPU) and Universal Software Radio Peripheral2 (USRP2) with URSP Hardware Driver (UHD) for SDR software modem and Radio Frequency (RF) transceiver, respectively. We have adopted UHD because UHD provides flexibility in the design of transceiver chain. Also, Cognitive Radio (CR) engine have been implemented by using libraries from UHD. Meanwhile, we have implemented the software modem in our system on GPU which is suitable for parallel computing due to its powerful Arithmetic and Logic Units (ALUs). From our experiment tests, we have measured the total processing time for a single frame of both transmit and receive LTE UL data to find that it takes about 5.00ms and 6.78ms for transmit and receive, respectively. It particularly means that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE UL system.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.1
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• pp.41-46
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• 2005

A new multiple description selective coding is proposed to overcome noisy channels. Our algorithm adopts an embedded coding scheme, in which subband coefficients are encoded one bit plane at a time using a non-adaptive arithmetic encoder. According to the importance ratio for each region, we code interest regions with more passes than background in order to reconstruct interest regions with higher quality. To overcome channel errors, we adopt multiple description scheme which adds controlled amounts of redundancy to the original data during the compression process. Proposed algorithm achieves better qualify compared with other algorithms especially in the circumstances where very low bit rate coding is required and some regions are more important than other regions.

• Journal of applied mathematics & informatics
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• v.19 no.1_2
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• pp.397-414
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• 2005

In the existing literature, most of the purchasing models were developed only for retailers problem ignoring the constraint of storage capacity of retailers shop/showroom. In this paper, we have developed a deterministic model of wholesaler-retailers' problem of single product. The storage capacity of wholesaler's warehouse/showroom and retailers' showroom/shop are assumed to be finite. The items are transported from wholesaler's warehouse to retailers' Own Warehouse (OW) in a lot. The customer's demand is assumed to be displayed inventory level dependent. Demands are met from OW and that spaces of OW will immediately be filled by shifting the same amount from the Rented Warehouse (RW) till the RW is empty. The time duration between selling from OW and filling up its space by new ones from RW is negligible. According to relative size of the retailers' existing (own) warehouse capacity and the demand factors, different scenarios are identified. Our objectives are to optimize the cost functions of wholesaler and two retailers separately. To solve this problem, a real coded Genetic Algorithm (GA) with roulette wheel selection/reproduction, whole arithmetic crossover and non-uniform mutation is developed. Finally a numerical example is presented to illustrate the results for different scenarios. To compare the results of GA, Generalised Reduced Gradient Method has been used for the problem. Also, a sensitivity analysis has been performed to study the variations of the optimal average cost with respect to the different parameters.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.415-418
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• 2008

Some embedded microprocessors do not have an FPU(Floating Point Unit) due to a circuit complexity and power consumption. The performance speed of MPEG-4 AAC decoder on this hardware environment would be slower than corresponding speed for playing back of the decoded results. Therefore, irritating and high-pitched noises are interleaved in the original the audio data. So, in order to play MPEG-4 AAC file on such PDA, a new algorithm that transforms floating-point arithmetic to one with integers, is needed. We have developed a transformation algorithm from floating-point operation to integer operation and implemented the PDA's AAC Player. We also show the efficiency of our proposed method with the experimental results.

• Speech Sciences
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• v.11 no.2
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• pp.181-192
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• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.