• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.5
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• pp.181-188
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• 2008

E-Science Grid is designed to cope with computation-intensive tasks and to manage a huge volume of science data efficiently. However, certain tasks may involve more than one grid can offer in computation capability or incur a long wait time on other tasks. Resource sharing among Grids can solve this problem with proper processing-integrity check via audit. Due to their computing-intensive nature, the processing time of e-Science tasks tends to be long. This potential long wait before an audit failure encourages earlier audit mechanism during execution in order both to prevent resource waste and to detect any problem fast. In this paper, we propose a Light-weight, Adaptive and Reliable Audit, LARA, of processing Integrity for e-Science applications. With the LARA scheme. researchers can verify their processing earlier and fast.

• Journal of information and communication convergence engineering
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• v.19 no.1
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• pp.42-47
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• 2021

Multimedia Authoring Tool is a tool for creating multimedia presentations. With this tool, a user can produce playable multimedia documents. A Multimedia Authoring Tool requires input in the form of a spatial layout and a temporal layout. Users can make many mistakes in creating multimedia presentations and verification is required in the Multimedia Authoring process in order to produce multimedia documents. In this study, two verification phases are proposed: Time Computation and Spatiotemporal Conflict Verification. In the experiment conducted for this study, two kinds of verification were carried out: The use of single-phase verification and the use of double-phase verifications. By using these two types of verification, it became easier to successfully detect errors in the spatial and temporal layouts, and the types of verification have also been successful in increasing the success of error detection.

• Current Optics and Photonics
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• v.6 no.1
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• pp.51-59
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• 2022

Holographic display technology is one of the promising 3D display technologies. However, the large amount of computation time required to generate computer-generated holograms (CGH) is a major obstacle to the commercialization of digital hologram. In various systems such as multi-depth head-up-displays with hologram contents, it is important to transmit hologram data in real time. In this paper, we propose a rapid CGH computation method by applying an arraying of a down-scaled hologram with the multiplication of a shifted concave lens function array. Compared to conventional angular spectrum method (ASM) calculation, we achieved about 39 times faster calculation speed for 3840 × 2160 pixel CGH calculation. Through the numerical investigation and experiments, we verified the degradation of reconstructed hologram image quality made by the proposed method is not so much compared to conventional ASM.

• The Journal of Korea Robotics Society
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• v.17 no.1
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• pp.16-24
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• 2022

This paper presents a method that can reduce the computational cost of the hierarchical quadratic programming (HQP)-based robot controller. Hierarchical controllers can effectively manage articulated robots with many degrees of freedom (DoFs) to perform multiple tasks. The HQP-based controller is one of the generic hierarchical controllers that can provide a control solution guaranteeing strict task priority while handling numerous equality and inequality constraints. However, according to a large amount of computation, it can be a burden to use it for real-time control. Therefore, for practical use of the HQP, we propose a method to reduce the computational cost by decreasing the size of the decision variable. The computation time and control performance of the proposed method are evaluated by real robot experiments with a 15 DoFs dual-arm manipulator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.101-113
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• 1986

In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

• International Journal of Computer Science & Network Security
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• v.23 no.6
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• pp.84-90
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• 2023

In this article the problem of computing floating-point reciprocal cube root functions is considered. Our new algorithms for this task decrease the number of arithmetic operations used for computing $1/{\sqrt[3]{x}}$. A new approach for selection of magic constants is presented in order to minimize the computation time for reciprocal cube roots of arguments with movable decimal point. The underlying theory enables partitioning of the base argument range x∈[1,8) into 3 segments, what in turn increases accuracy of initial function approximation and decreases the number of iterations to one. Three best algorithms were implemented and carefully tested on 32-bit microcontroller with ARM core. Their custom C implementations were favourable compared with the algorithm based on cbrtf(x) function taken from C ＜math.h＞ library on three different hardware platforms. As a result, the new fast approximation algorithm for the function $1/{\sqrt[3]{x}}$ was determined that outperforms all other algorithms in terms of computation time and cycle count.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.315-323
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• 1987

Generally, general-purpose image processing system is so expensive that not so many users easily can access the system. In this paper attemps have been made to design and describe a general and economical image processing system for real-time aplications such as image data compression, pattern recognition and target tracking. The system comprises an operator console, image data acquisition/display sistem and IBM PC/XT. The system also utilizes a high speed Fairchild 16-bit microprocessor with ALU speed of 375 nsec for system control, algrithm execution and user computation. The system also can digitize /display a 256x 256x 8 bit image in real time and store two frames of images. All image pixels are directly accessible by the microprocessor for fast and efficient computation. Some experimental and illustrative results such as target tracking are presented to show the efficient performance of the system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• International Journal of Control, Automation, and Systems
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• v.4 no.5
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• pp.539-544
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• 2006

An $H_2$ filter is derived for time delay systems, where there are time delay terms in the state and in the output. A method to compute the $H_2$ norm of time delay systems is proposed. Based on the $H_2$ norm computation method, an $H_2$ filter design is formulated as a nonlinear optimization problem.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.956-959
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• 2005

The overall goal of this thesis is to develop a new algorithm based on the octree model for geometric and mechanistic milling operation at the same time. Most commercial machining simulators are based on the Z map model, which has several limitations in terms of achieving a high level of precision in five-axis machining simulation. Octree representation being a three-dimensional (3D) decomposition method, an octree-based algorithm is expected to be able to overcome such limitations. With the octree model, storage requirement is reduced. Moreover, recursive subdivision is processed in the boundaries, which reduces useless computations. To achieve a high level of accuracy, fast computation time and less memory consumption, the advanced octree model is suggested. By adopting the supersampling technique of computer graphics, the accuracy can be significantly improved at approximately equal computation time. The proposed algorithm can verify the NC machining process and estimate the material removal volume at the same time.