• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1087-1094
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• 2007

In this paper, we propose a new peak-to-average power ratio (PAPR) reduction scheme of orthogonal frequency division multiplexing (OFDM) system, called a modified selected mapping (SLM) scheme, which considerably reduces the computational complexity with keeping the similar PAPR reduction performance compared with the conventional SLM scheme. The proposed scheme is analytically and numerically evaluated for the OFDM system specified in the IEEE 802.16 standard. For the OFDM system with 2048 subcarriers, the proposed scheme with 4 binary phase sequences can reduce the complex multiplications by 63.5% with the similar PAPR reduction compared with the SLM scheme with 16 binary phase sequences.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1339-1345
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• 2007

An important drawback in Lattice Reduction (LR) aided detectors has been investigated. For the solution, an improved LR aided detection with ignorable complexity overhead is proposed for MIMO system, where the additional correction operation is performed for the case of unreliable symbol decision. We found that LR aided detection errors mainly occur when the lattice points after the inverse lattice transform in the final step fall outside the constellation point set. In the proposed scheme, we check whether or not the lattice point obtained through LR detection is out of constellation. Only for the case of out of constellation, we additionally perform ML search with reduced search region restricted to the neighboring points near to the obtained lattice points. Using this approach, we can effectively and significantly improve the detection performance with just a slight complexity overhead which is negligible compared to full searched ML scheme. Simulation results show that the proposed scheme achieves the detection performance near to that of the ML detection with a lower computational complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.11
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• pp.1051-1059
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• 2013

This paper proposes a complexity reduced list sphere decoding (LSD) scheme for joint iterative soft detection scheme for coded MIMO system. The conventional LSD scheme is based on searching the candidates with a fixed radius. However, once the candidate list is full, it is highly probable that the radius can be reduced. By reducing the radius, the complexity can be also reduced. We propose a simple and efficient radius update method for complexity reduction of list version sphere decoding and its application to iterative soft MIMO detection. We evaluate the performance of the proposed scheme with a joint soft-input-soft-ouput iterative MIMO detection in combination with turbo codes. Simulation results show that the proposed methods provide substantial complexity reduction while achieving similar bit error rate (BER) performance as the conventional LSD scheme.

• Journal of Korea Multimedia Society
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• v.14 no.10
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• pp.1238-1242
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• 2011

An efficient architecture for the reduction of complexity in forward quantization of H.264/AVC is presented in this paper. Since the multiplication operation in forward quantization plays crucial role in complexity of algorithm. More efficient quantization architecture with simplified high speed multiplier is proposed. It uses the modification of the quantization operation and the high speed multiplier is applied for simplification of quantization process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1259-1262
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• 2006

In this paper, we propose a modified cubic convolution interpolation for the enlargement or reduction of digital images using a pixel difference value. The proposed method has a low complexity: the number of multiplier of weighted value to calculate one pixel of a scaled image has seven less than that of cubic convolution interpolation has sixteen. We use the linear function of the cubic convolution and the difference pixel value for selecting interpolation methods. The proposed method is compared with the conventional one for the computational complexity and the image quality. The simulation results show that the proposed method has less computational complexity than one of the cubic convolution interpolation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.411-412
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• 2006

In this paper, we proposed a fast algorithm for inter prediction included the most complexity in H.264/AVC. It decide search range according to direction of predicted motion vector, and then perform adaptive candidate spiral search. Simultaneously, it perform motion estimation of variable loop with threshold for variable block size. Conclusively, it is implemented in JM FME with high complexity applying to rate-distortion optimization. Experimental results show that significant complexity reduction is achieved while the degradation in video quality is negligible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.86-93
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• 2009

We investigate lattice-reduction-aided precoding techniques for multi-user multiple-input multiple-output (MIMO) channels. When assuming full knowledge of the channel state information only at the transmitter, a vector perturbation (VP) is a promising precoding scheme that approaches sum capacity and has simple receiver. However, its encoding is nondeterministic polynomial time (NP)-hard problem. Vector perturbation using lattice reduction algorithms can remarkably reduce its encoding complexity. In this paper, we propose a vector perturbation scheme using Seysen's lattice reduction (VP-SLR) with simultaneously reducing primal basis and dual one. Simulation results show that the proposed VP-SLR has better bit error rate (BER) and larger capacity than vector perturbation with Lenstra-Lenstra-Lovasz lattice reduction (VP-LLL) in addition to less encoding complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6A
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• pp.551-557
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• 2011

We investigate lattice-reduction-aided precoding techniques using Look-Up table (LUT) for multi-user multiple-input multiple-output(MIMO) systems. Lattice-reduction-aided vector perturbation (VP) gives large sum capacity with low encoding complexity. Nevertheless lattice-reduction process based on the LLL-Algorithm still requires high computational complexity since it involves several iterations of size reduction and column vector exchange. In this paper, we apply the LUT-aided lattice reduction on VP and propose a scheme to generate the LUT efficiently. Simulation results show that a proposed scheme has similar orthogonality defect and Bit-Error-Rate(BER) even with lower memory size.