• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.377-384
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• 2009

In this paper, leakage current sensing module of SoC(System on Chip)type and real time monitoring system under consideration of electromagnetic interface in power trunk line are developed. The first, leakage current sensing module of SoC type under consideration of electromagnetic interface is developed, and the developed sensing module of SoC type is composed of leakage sensing part, power supply part, interface part, communication part, AD(Alternating current to Direct current)convert part and amplification part. And also the electromagnetic compatibility is evaluated by conduction and radiation of EMI(Electromagnetic Interference) for developed sensing module. The developed system can have confidence, stability and do energy saving under mixed electric circumstance of the low voltage communication device and high voltage equipment. The second, the real time remote monitoring system is developed using designed wire and wireless communication module with leakage current sensing module of SoC type. The developed real time remote monitoring system can monitor sensing state, occurrence state of leakage current and alarm for each step etc.. And the device configuration, PCB layout for leakage current sensing module of system on chip type and the experiment configuration in consideration of EMI are presented. Also the measurement results of conduction and radiation for EMI are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.344-352
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• 2020

Covertness and performance are very important design goals in the underwater communications. To satisfy both of them, we proposed efficient underwater communication model which combined multiband and direct sequence spread spectrum method in order to improve performance and covertness simultaneously. Turbo coding method with 1/3 coding rates is used for channel coding algorithm, and turbo equalization method which iterately exchange probabilistic information between equalizer and decoder is used for receiver side. After optimal threshold value was set in Rake processing, this paper analyzed the performance by varying the number of chips were 8, 16, 32 and the number of bands were from 1 to 4. Through the simulation results, we confirmed that the performance improvement was obtained by increasing the number of bands and chips. 2~3 dB of performance gain was obtained when the number of chips were increased in same number of bands.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.681-684
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• 2008

In this paper, triple band mobile chip antenna for DCS($1.71{\sim}1.88GHz$) / PCS($1.75{\sim}1.87GHz$) / UPCS($1.85{\sim}1.99GHz$) on PCB Layout is fabricated. As designed and fabricated antenna is loaded PCB layout, that plate a both side at two independence patterns(upper & lower) to reduce the size and a capacitor for DCS, PCS, UPCS band is proposed. The antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is the defect of chip antenna is improved. Bandwidth of fabricated antenna to VSWR less than 2 is satisfied and all bandwith is acquired 15.1 % at $1.71GHz{\sim}1.99GHz$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.128-133
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• 2010

We investigate the optimal chip rate of power or rate adapted direct-sequence code division multiple access (DS/CDMA) communication systems in Nakagami fading channels. We find that the optimal chip rate that maximizes the spectral efficiency depends upon both the channel parameters, such as multipath intensity profile (MIP) and line-of-sight (LOS) component, and the adaptation scheme itself. With the rate adaptation, the optimal chip rate is less than $1/T_m$, irrespective of the channel parameters, where $1/T_m$ is multipath delay spread. This indicates that with the rate adaptation, correlation receiver achieves higher spectral efficiency than RAKE receiver. With the power adaptation, however, the optimal chip rate and the corresponding number of tabs in RAKE receiver are sensitive to MIP and LOS component.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.999-1008
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• 2012

Unlike the existing CMOS chip, ISB (Intelligent Silicon Bead) is new concept biochip equipped with optical communication and memory function. It uses the light for power of SoC CMOS and interface with external devices therefore it is possible to miniaturize a chip size and lower the cost. This paper introduces an input protocol and a design of the low power and the low area to transfer the power and the signal through a single optical signal applied from external reader device to bead chip at the same time. It is also verified through simulation and measurement. In addition, low-power PROM is designed for recording and storing ID of a chip and it is successful in obtaining the value of output according to the optical input. Through this study, a new type biochip development can be expected by solving high cost and a limit of miniaturizing a chip area problem of an existing RFID.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2210-2216
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• 2007

In this paper, triple-band plastic chip antennas for mobile terminal are investigated. Plastic chip antenna is composed of Foamex material with circle of PVC(Polyvilyl chloride). For its electric characteristics, the dielectric constant is 1.9, the insulation intensity is 112KV/cm. Plastic chip antennas are don't tend to break easily against to external shock, have more gain and efficiency than ceramic chip antennas. Triple-band plastic chip antennas of four type are implemented and experimented. From the experiments results, the antenna resonate at the triple-band, the gain of the antennas has about above -2dB, the pattern is ommidirectional the same as the conventional antennas. So, the antennas realized with Foamex material will be application for mobile phone antenna operated at the triple band which is cellular band and Korea-PCS band and ISM band or the antenna for other wireless communication system.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.97-100
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• 1996

In this paper, 3-terminal EMI filter for communication was studied. EMI filter for communication combining Ferrite bead with 3-terminal capacitor was constructed with T-type. We was able to control resonance frequency with chip capacitor value and attenuation characteristics by Ferrite bead properties.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.