• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.321-326
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• 2015

Smart metering is one of the most implementable internet-of-thing service. In order to implement the smart metering, a wireless communication network should be newly designed and evaluated so as to satisfy quality-of-service of smart metering. In this paper, we consider a wireless network for the smart metering implemented with multi-purpose wireless chips and channel coding-functioned micro controllers. Especially, channel coding is newly adopted to improve successful frame transmission probability. Based on the successful frame transmission probability, average transmission delay and delay violation probability are analyzed. Using the analytical results, service coverage expansion is evaluated. Through the delay analysis, service feasibility can be verified. According to our results, channel coding needs not to be utilized to improve the delay performance if the smart metering service coverage is several tens of meters. However, if more coverage is required, chanel coding adoption definitely reduces the delay time and improve the service feasibility.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.10-20
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• 1994

This paper presents a CATV SMS (Status Monitoring System) using HDLC (High Level Data Link Contorl) protocol and the system implementation.The system specifications were derived from the analysis of technical status and requirement of the domestic CATV industry. For the interoperability with a global network management system in the future, HDLC protocol was adopted in the system. The system performance was improved by using the communication controller chip and the large data buffer. For reducting the communication problems induced by accumulated noise in up-stream data channels, the system was designed that the different communication channel can be assigned to each proper mass of terminal. The operating software was designed with menu driven user interface and have various functions for the convenience of users. The test result of the implemented system at the experimental network showed good performance and suitability for a coaxial CATV Status Monitoring System.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.485-486
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• 2006

This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1313-1315
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• 1996

This paper presents a new method to obtain more stable and precise A/D conversion for remote sensing use. Hardware is designed to compensate offset voltage and drift & temperature characteristics, as well as to perform dual slop A/D converter by using single chip microprocessor. Serial communication program which is based on ASCII code commands is also developed to add initial setup & calibration functions as well as to perform A/D data communication. Proposed method will give a good applications to the industrial field where a high precision remote sensing is required.

• Journal of Sensor Science and Technology
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• v.22 no.6
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• pp.439-443
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• 2013

A wireless optical fiber interferometer arterial pulse wave sensor system is developed for remote sensing. The wireless optical fiber sensor system consists of Zigbee communication modules and an optical fiber interferometer arterial pulse wave sensor. The optical fiber arterial pulse wave sensor is an in-line Michelson interferometer enclosed with steel reinforcement in a heat-shrinkable tube. The Zigbee communication modules are composed of an ATmega128L microprocessor and a CC2420 Zigbee chip. The arterial pulse waves detected by the optical fiber sensor were transmitted and received via the Zigbee communication modules. The experimental results show that the wireless optical fiber sensor system can be used for monitoring the arterial pulse waves remotely.