• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.313-318
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• 2012

This paper presents an automatic system to detect variety of faults from fine pitch COF(chip-on-film) which is less than $30{\mu}m$. Developed system contains circuits and technique to detect fast various faults such as hard open, hard short, soft open and soft short from fine pattern. Basic principle for fault detection is to monitor fine differential voltage from pattern resistance differences between fault-free and faulty cases. The technique uses also radio frequency resonator arrays for easy detection to amplify fine differential voltage. We anticipate that proposed system is to be an alternative for conventional COF test systems since it can fast and accurately detect variety of faults from fine pattern COF test process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.245-252
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• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1261-1266
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• 2009

In this paper, triple band mobile chip antenna for DCS(1.71${\sim}$1.88GHz) / PCS(1.75${\sim}$1.87GHz) / UPCS(1.8S${\sim}$1.99GHz) on PCB Layout is designed. To analyze the characteristics of the designed antenna, we used commerical simulation tool(HFSS). Triple and wide band characteristic could be realized the measured bandwidth(V.S.W.R<2.0) of the designed antenna operated in 1.71GHz${\sim}$1.99GHz. The size of the designed antenna is about 19mm${\times}$4mm${\times}$1.6mm, narrow bandwidth which is a defect of chip antenna is improved. And its experimental results were a good agreement with simulation performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.10
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• pp.907-913
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• 2015

This work presents a method to predict the near magnetic field distribution on the digital switching circuit mounted on PCB using co-simulation of circuit and electromagnetic fields. The proposed method first obtains the normalized near field distribution by exciting the signal and power ports of the switching circuit using sinusoidal sources. Then the real near magnetic field distribution is determined by weighting the normalized field distribution using the current spectrum of the switching circuit. To confirm the proposed method, a switching IC with a ring oscillator and a output buffer is fabricated and measured in the form of chip-on-board. The surface magnetic field distribution is measured using a magnetic probe above the PCB and compared with the simulation results. Experimental results show the correspondence between simulation and measurement results within 10 dB up to fifth harmonics.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.393-398
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• 2009

In this paper, we study the design and implementation of an auto recognition system by using wireless sensor node. RFID system has a limited communication range and communication network is damaged, it is impossible to communicate. Therefore, easy installation and low cost wireless system are required in an area where the installation of communication between RFID system and monitoring system is difficult, or a portable RFID system is installed. The auto recognition system in this study is implemented by the combination of 13.56MHz RFID system using MLX12115 RFID chip of Melexis company and wireless sensor node system using CC2420 Zigbee chip of Chipcon company. As a result, we develop an auto recognition system which makes it possible to get tag's information wirelessly. Also, it has a simple circuit structure and is small in size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.205-209
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• 2000

Modem wireless communication equipments provides various multimedia and aims at the development of low-power, minimum size and weight, and low-cost implimentations. Because of the heterodyne architecture which was invented many decades ago in the wireless communication system using too many components, it was difficult to make it small, compact and On-Chip so it does not proper for future communication. That gives rise a new developing architecture, so called, Direct Conversion. Because The Direct Conversion down-converts the wireless frequency band to baseband directly, it does not need using additive components and has a merit of reduction in power dissipation. We describes the Direct Conversion architecture and DC-Offset, which must be solved, theorectically and predicts system performance enhancement when adopt the AC-Coupling method.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.213-219
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• 2010

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, MC-CDMA, CDMA and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System one Chip) technology, thus a noble modem design proper for SoC technology is necessary. For high speed data transmission of 4G mobile communication services, OFDM scheme has to be applied. But, an OFDM signal consists of a number of independently modulated subcarriers, and superposition of these subcarriers cause a problem that can give a large PAPR. In this paper, a noble modem design for 4G mobile communication services and PAPR reduction method for solving the PAPR problem are proposed.