• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.137-140
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• 2005

A frequency synthesizer of 10 GHz $\sim$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz $\sim$ 11 GHz, so we lower the frequency to 625 MHz $\sim$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• International Journal of Internet, Broadcasting and Communication
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• v.7 no.2
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.758-761
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• 1991

Using one chip microcontroller 87Cl96 (On chip EPROM type) and EPLD (Erasable & Programable Logic Device), an implantable control system to drive pendulum type electromechanical total artificial heart was developed. This control system consists of 4 parts, main management system, motor driver with power regulator, state monitoring system and communication part. The main system has the functions for speed detection, PI(proportional and integration) control, PWM generation, communication and analog data processor. Two kinds of power system were used and separated by 8 photo coupler arrays to improve the system stability. The performances of each compartments were compared with our previous z80 microprocessor based control system and good correspondences was shown. Logic power consumption was reduced to a one third of our previous controller. Using mock circulation tests, the overall performances of control system are evaluated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.96-99
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• 2002

This paper describes the implementation of a SoC(system on a Chip) for a mult communication terminal in ISDN network and also reviews the developed software struct service procedures which are working on the SoC. And finally this paper descr： of an ISDN terminal equipment using the implemented SoC and terminal software.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.59-64
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• 2009

In this paper, we represent characteristics and equivalent circuit of donut type resonator of defected ground structure (DGS), and can control resonant frequency with chip capacitor. In General, DGS operates like with parallel LC resonator. We found out variation of resonance frequency when capacitor is placed on slot of DGS. If the chip capacitor replace with varactor diode, the resonance frequencies can be controlled by voltage. This tualable resonator can apply to voltage controlled oscillator and tunable bandpass filter.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.5
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• pp.575-582
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• 2014

One of the most important decision making is which product's components should make in-house and which should they outsource. This paper suggests a framework to solve above question. This paper applies to LCD TV industry with AHP analysis. The results shows that Scaler chip, LCD panel, MPEG decoder, and Video decoder are important components. Samsung Electronics turn out make in-house these core component. This research will be a good guideline for selecting core component.

• Journal of information and communication convergence engineering
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• v.17 no.4
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• pp.279-284
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• 2019

This paper presents processing-node status-based message scattering and gathering algorithms for multi-processor systems on chip to reduce the communication time between processors. In the message-scattering part of the message-passing interface (MPI) scatter function, data transmissions are ordered according to the proposed linear algorithm, based on the processor status. The MPI hardware unit in the root processing node checks whether each processing node's status is 'free' or 'busy' when an MPI scatter message is received. Then, it first transfers the data to a 'free' processing node, thereby reducing the scattering completion time. In the message-gathering part of the MPI gather function, the data transmissions are ordered according to the proposed linear algorithm, and the gathering is performed. The root node receives data from the processing node that wants to transfer first, and reduces the completion time during the gathering. The experimental results show that the performance of the proposed algorithm increases at a greater rate as the number of processing nodes increases.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.539-542
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• 1990

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1475-1482
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• 2009

In this paper, a computer simulation is developed for isotachophoretic protein separation in a serpentine micro channel for optimal lab on a chip design using 2D Finite Element Method. This 2D ITP model is composed of 5 components such as hydrochloric acid as Leader, caproic acid as terminator, acetic acid and benzoic acid as two proteins, and histindine as background electrolyte. The computer model is based on mass conservation equation for 5 components, charge conservation equation for electric potential, and electro neutrality condition for pH calculation. For the validation of the 2D spatial ITP model, the results are compared with the Simul5 developed by Bohuslav Gas Group. The simulation results are in a good agreement in a ID planar channel. This proves the precision of our model. The 2Dproteinseparation is conducted in a 2D curved channel for Lab on a chip design and dispersions of proteins are revealed during the electrophoretic process in a curved shape.