• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.141-145
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• 2008

When the current flows to parallel lines with different length, it is researched that the radiation is occured by the common-mode current radiates, and the small light weight antenna composed of dual elements by using the principle is proposed. However, there is a problem in production about this antenna because this liner antenna is structured by combining with wires. In this paper, we improved this liner antenna, and designed the plane antenna composed of dual elements with different length in the plane printed board to produce and to design easily. Furthermore, the antenna with the wide-band characteristic is also designed in the same board. The radiation pattern is similar to the dipole antenna on account of designing the triangular patch S, the notch and two tapers in patch S, the notch and two tapers in the antenna element. In result, it was able to design the antenna working wider band-width(the bandwidth ratio about 58%, $VSWR{\le}2$).

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.452-457
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• 1998

This paper deal with problems of leakage current, shaft voltage, bearing current, and EMI, in valiable-speed AC drives. The originating mechanism is illustrated with a high-frequency equivalent circuit. Reduction methods are classified in to six categories based on the equivalent circuit. Some experimental results show that a common-mode transformer (CMT) and a common-noise canceler (ACC) can solve the problems, which have been proposed the authors.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.9
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• pp.52-59
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• 2007

Fuel injection system greatly affects the performance of a direct injection diesel engine. A common rail injection system was introduced to satisfy the stringent emission standards, low fuel consumption, and low noise in recent years. The performance of a common-rail fuel injection system is strongly influenced by the injector characteristics. The common rail injector has evolved in order to improve its injection performance. The piezo-actuated injector is more suitable for common rail injection system due to its fast response and is expected to replace current solenoid-operated injector. In this study, nonlinear mathematical models are proposed for the solenoid-operated and the piezo-actuated injectors for control applications. Based on these models, the injection rate, which is one of the most important factors for the injection characteristics, is estimated using sliding mode observer. The simulation results and the experimental data show that the proposed sliding mode observers can effectively estimate the injection timing and the injection rate for both common-rail injectors.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.91-94
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• 2002

This paper presents a novel active common-mode EMI filter for the PWM inverter application. The proposed filter is based on the current sensing and compensation circuit and it utilizes a fast transistor amplifier for the current compensation. The amplifier utilizes an isolated low-voltage dc power supply for its biasing and it is possible to construct the active filter independent of the source voltage of the equipment. Thus the proposed active filter can be used in any application regardless of its working voltage. The effectiveness of the proposed circuit is verified by experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.509-516
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• 2015

The overmodulation characteristics of a carrier-based medium vector pulse width modulation (CBMVPWM) are examined in this study. CBMVPWM can completely eliminate leakage currents in a three-phase, three-level inverter using only the switching states with the same common mode voltage even in an overmodulation operation. The analytic equations for the magnitude of the output voltage and the switching frequency are derived for overmodulation operation, and the effect of dead time on the leakage current is demonstrated. This study presents the operating principle of CBMVPWM, basic overmodulation features, and simulations and experiments for operating verification.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.79-85
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• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.195-196
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• 2012

In recent years, in an effort to improve the efficiency and the power density of the front-end power factor correction(PFC), the interleaving of multiple converter is employed. The conventional interleaved continuous conduction mode(CCM) boost PFC converter requires input and output voltage sensing and three current sensing to obtain current balancing between modules. In this paper, the interleaved CCM PFC converter based on modulated carrier control is proposed. With the proposed method, two phase interleaved PFC can be realized simply without line voltage sensing resistor and can achieve current balancing without additional current sensing resistor on common return path. The simulation studies are carried out to verify the effectiveness of the proposed control scheme.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1217-1226
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• 2015

In a grid-connected photovoltaic (PV) system, the traditional Z-source inverter uses a low frequency transformer to ensure galvanic isolation between the grid and the PV system. In order to combine the advantages of both Z-source inverters and transformerless PV inverters, this paper presents a modified single-phase transformerless Z-source PV grid-connected inverter and a corresponding PWM strategy to eliminate the ground leakage current. By utilizing two reversed-biased diodes, the path for the leakage current is blocked during the shoot-through state. Meanwhile, by turning off an additional switch, the PV array is decoupled from the grid during the freewheeling state. In this paper, the operation principle, PWM strategy and common-mode (CM) characteristic of the modified transformerless Z-source inverter are illustrated. Furthermore, the influence of the junction capacitances of the power switches is analyzed in detail. The total losses of the main electrical components are evaluated and compared. Finally, a theoretical analysis is presented and corroborated by experimental results from a 1-kW laboratory prototype.