• 한국전기전자재료학회논문지
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• 제23권4호
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• Journal of Power Electronics
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• 제17권1호
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• pp.88-95
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• 2017

To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• ETRI Journal
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• 제31권2호
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.650-654
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• 1999

In this paper, author describe the simulation results concerning the period doubling bifurcation route to chaos of DC/DC boost converter under current mode control to show that it is common phenomena on switching regulator when parameters are improperly chosen or continuously varied beyond the ensured region by system designer. Bifurcation diagrams of periodic orbits of inductor current and capacitor voltage of DC/DC boost converter are plotted with sampled data at moment of each clock pulse causing switching on. DC/DC boost converter studied on this paper is modelled by its state space equations as per switching condition under continuous conduction mode. Current reference signal and capacitance are chosen as the bifurcation parameters and those are varied in step for iterative calculation to find bifurcation points of periodic orbits of state variables.

• Journal of Power Electronics
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• 제18권5호
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• pp.1458-1469
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• 2018

This paper proposes a novel common-mode voltage (CMV) elimination (CMV-EL) method based on model predictive control (MPC) to eliminate CMV for three-level T-type inverters (3LT2Is). In the proposed MPC method, only six medium and one zero voltage vectors (VVs) (6MV1Z) that generate zero CMV are considered as candidates to perform the MPC. Moreover, the influence of dead-time effects on the CMV of the MPC-based 6MV1Z method is investigated, and the candidate VVs are redesigned by pre-excluding the VVs that will cause CMV fluctuations during the dead time from 6MV1Z. Only three or five VVs are included to perform optimization in every control period, which can significantly reduce the computational complexity. Thus, a small control period can be implemented in the practical applications to achieve improved grid current performance. With the proposed CMV-EL method, the CMV of the $3LT^2Is$ can be effectively eliminated. In addition, the proposed CMV-EL method can balance the neutral point potentials (NPPs) and yield satisfactory performance for grid current tracking in steady and dynamic states. Simulation and experimental results are presented to verify the effectiveness of the proposed method.

• Journal of Power Electronics
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• 제19권2호
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• pp.403-412
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• 2019

Aiming at the problems of large dv/dt and di/dt in traditional single-ended converters and high electromagnetic interference (EMI) noise levels, a single-ended isolated converter using the secondary resonance technique is proposed in this paper. In the proposed converter, the voltage stress of the main power switch can be reduced and the voltage across the output diode is clamped to the output voltage when compared to the conventional flyback converter. In addition, the peak current stress through the main power switch can be decreased and zero current switching (ZCS) of the output diode can be achieved through the resonance technique. Moreover, the EMI noise coupling path and an equivalent model of the proposed converter topology are presented through the operational principle of the proposed converter. Analysis results indicate that the common mode (CM) EMI noise and the differential mode (DM) EMI noise of such a converter are deduced since the frequency spectra of the equivalent controlled voltage sources and controlled current source are decreased when compared with the traditional flyback converter. Furthermore, appropriate parameter selection of the resonant circuit network can increase the equivalent impedance in the EMI coupling path in the low frequency range, which further reduces the common mode interference. Finally, a simulation model and a 60W experimental prototype of the proposed converter are built and tested. Experimental results verify the theoretical analysis.

• 전기학회논문지P
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• 제62권2호
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• pp.72-78
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• 2013

In this study, samples from the site where there occurred unbalanced current when cable routing were analyzed, and the simulation program for electric power system analysis, PSCAD/EMTDC, was used to calculate the current unbalance on cable routing. Based on electromagnetic finite element analysis(FEA), electromagnetic parameters enabled the interlocking with COMSOL for the calculation of allowable current ampacity and magnetic filed distribution. This then led to modeling unbalanced current between common modes using the unbalanced current analysis program, thereby comparing and discussing the results from both. The analyzed model is a common mode 2 parallel circuit, which is a basic model for cable routing, and by arranging cables in various ways, the arrangement with the least current unbalance was suggested, which would, in the future, prevent earth faults and extend life for the whole cable.

• 한국전자파학회논문지
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• 제20권9호
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• pp.900-905
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• 2009

본 논문에서는 전류 블리딩(bleeding)과 입력 인덕티브 직렬-피킹을 이용한 공통 드레인 귀환(Common Drain Feedback: CDFB) CMOS 광대역 저잡음 증폭기(Low Noise Amplifier: LNA)를 설계하였다. 캐스코드 증폭기와 귀환 증폭기를 DC 결합하여 블리딩 전류의 조정을 통해 LNA의 이득과 잡음 지수(Noise figure: NF)의 동적 제어를 실현하였다. 제작한 LNA는 2.5 GHz의 대역폭에서, 고이득 영역은 $1.7{\sim}2.8\;dB$ NF와 17.5 dB 이득, 그리고 27 mW의 전력 소비를 보이고, 저 이득 영역은 $2.7{\sim}4.0\;dB$ NF와 14 dB 이득, 그리고 1.8 mW의 전력 소비를 보인다.

• 한국통신학회논문지
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• 제17권1호
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• pp.68-79
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• 1992

고속 아날로그 시스템,위성통신시스템, video signal processing 및 processing 및 optical fiber interface 회로등에서 높은 전자이동도로 인하여 고주파 툭성이 우수한 GaAs 연산 증폭기는 필수적인 구성 요소이다. 하지만, 낮은 전달컨덕턱스 및 low frequency dispersion등의 현상 때문에 높은 전압이득을 얻을 수 없다는 단점을 가지고 있다. 따라서 본 논문에서는 GaAs MESFETfmf 이용한 증폭기의 이득을 증가시키기 위한 기법을 비교분석하고 기존의 전류미러와 새로운 구성의 전류 미러를 설계하여 회로의 안정화를 꾀하였다. 높은 차동전압이득을 얻기 위하여 단일 증폭기의 bootstrap 이득증가기법을 이용하여 차종입력 회로를 구성하였으며, 회로의 안정도 및 우수한 주파수 특성을 얻기 위하여 common mode feedback을 사용하였다. Pspice를 통한 시뮬레이션 결과 설계된 회로의 이득이 18.6dB 향상되었고 안정도 및 주파수 특성면에서 우수함을 확인할 수 있었다.