• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.2015-2024
• /
• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4A
• /
• pp.336-344
• /
• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.637-637
• /
• 1997

In this paper, format conversion filters are proposed, which have advantages in hardware implementation compared to the ones proposed in MPEG-4 Video Verification Model. since each coefficients of the proposed filters is constrained to have less than two non-zero digits in minimal signed digit representation, multiplication of input and the coefficient can be implemented by a single adder. As a result, the proposed filters have advantages in hardware complexity and speed, compared to the filters which are usually implemented by integer multiplier or carry save adders. Six kinds of filters are proposed in MPEG-4 Video Verification Model for size conversion of 2:1, 4:1, 5:3 and 5:6. We design 5 filters for the same purpose and compare the performance. The remaining one is very simple to implement. For comparing the filtering performance, we first compare the results of sine wave frequency conversion as an indirect but meaningful comparison. Second. We compute the PSNR of the images obtained from the proposed filters and the ones proposed by MPEG, with reference to the images obtained by using double precision arithmetic and high order filter. The results show that the performance of the proposed filters is almost the same as that of the filters proposed by MPEG. In conclusion, the peroformance of the proposed filters is comparable to that of the ones in MPEG-4, while requiring lower hardware complexity and providing high operating speed.

• Journal of the Korean Regional Science Association
• /
• v.34 no.4
• /
• pp.61-74
• /
• 2018

This study aims to analyze the convergence change of smart city industries in Korea. Industries of Smart city can be defined ICTs and Knowledge embedded construction industry. The input output model and structural path analysis have been done using the input output tables published by Bank of Korea in 1980 and 2014. GDP deflator was applied to the input output tables. 403 industries were reclassified into 27 industries and 8 industries categories: Agriculture and Mining(AM), Non-IT Manufacture(NITM), IT Manufacture(ITM), Energy Supply(EnS), Construction as smart city(C), IT Service(ITS), Knowledge Service(KS), Etc. Service(EtS). The results are as follows; First, the input output coefficient analysis showed that The information and communication service industry(ITS) and the energy supply industry(EnS) have increased input to the construction industry(C). On the other hands, knowledge service industry(KS) and etc. service industries(EtS) decreased. Second, the multiplier analysis revealed that construction industry(C) led by smart city had a great influence on ITS, EnS, ITM and NITM directly and indirectly. Furthermore, The IT industry had the biggest change from 1980 to 2014. Third, the smart city industry has created a new convergence of 117, and it has been leading to segmentation of the structure. Change of convergence has been proceeding mainly in the ITS and EnS, NITM, ITM industries.