• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.7
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• pp.302-307
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• 2002

Digital watermarking is the technique, which embeds an invisible signal including signal including owner identification and copy control information into multimedia data such as audio, video, and images for copyright protection. A new MPEG watermark embedding algorithm using complex block effect based on the Human Visual System(HVS) is introduced in this paper. In this algorithm, $8{\times}8$ dark blocks are selected, and the watermark is embedded in the DC component of the discrete cosine transform(DCT) by using quantization and modulus calculation. This algorithm uses a blind watermark retrieval technique, which detects the embedded watermark without using the original image. The experimental results show that the proposed watermark technique is robust against MPEG coding, bitrate changes, and various GOP(Group of Picture) changes.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.20-23
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• 1996

The block matching algorithm for the motion estimation is relatively simple to implement, and thus widely applied in image sequence coding such as H.261, MPEG- I and MPEG-2. Most techniques of the block matching method use fixed-size blocks for the motion estimation. And their success relies on the assumption that the motion within each block is uniform. But if the block size is increased to reduce the number of motion vectors for high data compression, the estimated image brings about many errors. In this paper, the variable-sized blocks are used to solve this problem. And the top down method is used to select the block size.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.370-377
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• 2003

MC-CDMA is a digital modulation technique where a single data symbol is transmitted at multiple subcarriers which are orthogonal to each other. With this technique, frequency diversity can be achieved. The performance of MC-CDMA systems is analyzed, when data is transmitted over multi-path and Doppler fading channel. The performance of this technique, gauged by the average bit error rate, is numerically analyzed for the system with the application of antenna diversity and error control coding.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.158.1-158
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• 2001

An algorithmic gray code analog-to-digital converter (ADC), which is based on gray coding, is proposed in this article. The realization method makes use of a MOS triangular function circuit to provide a high-speed operation and low accumulated error. The proposed ADC is simple, small in size and suitable for fabrication using a standard CMOS process. Simulation results showing the performances of the proposed circuit are also included.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.70.1-70
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• 2002

In the fuzzy applications and theories, it is very important to consider how to design the optimal fuzzy model from short training data, in order to construct the reasonable fuzzy model for identifying the practical process. There are several concerns to be confirmed for efficient fuzzy model design. One of concern is the optimization problem of the fuzzy model. In various applications, the genetic algorithm is widely applied to obtain optimal fuzzy model and other cases that adopt evolutionary mechanism of the nature. If we use natural selection and multiplication operation of the genetic algorithm, early convergence to local minimum can be occurred. In other word, we can find only optimum...

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.181-184
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• 2003

Recently, the fieldbus becomes an indispensable component for many automated systems. In the fieldbus system, realtime data containing sensor values and control commands has a tendency to rapidly lose its value as time elapses after its creation. In order to deliver these data in time, the fieldbus network should be designed to have short delay compared to the maximum allowable delay. Because the communication delay is affected by performance parameters such as target rotation timer of token passing protocol, it is necessary to select proper parameter settings to satisfy the real-time requirement for communication delay. This paper presents the timer selection method for Profibus token passing networks using genetic algorithm (GA) to meet the delay requirements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.73-85
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• 1993

This paper presents a design and implementation of CAD(Computer-Aided Design) system with tools and design environments for IC(Intergrated Circuits)design. The CAD system can be easily installed in various sites with limited resources, since most CAD tools and design environments are available in the public-domain and Unix & X Window-based PC-386 and Workstation is used for the hardware platform. In order to improve the flexibility of the CAD system, objects are defined in the context of tools and environments` and object tables are programmed to describe the integration of CAD tools and design environments. During the execution, tool-objects deal with intertool communication and round-robin mechanism to incrementally control the execution of CAD tools. The IC design of LPC(Linear Predictive Coding) Speech Synthesizer is carried out to find out improvements and bugs of the CAD system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.246-251
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• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.65-70
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• 2004

본 논문에서는 화면간 상관성을 이용한 최적의 비트 할당 알고리즘을 제안한다 제안된 알고리즘은 기존의 Q2 비트율 제어 알고리즘을 기반으로 하며, 인트라(Intra) 화면에 대한 비트할당과 인터(Inter) 화면에 대한 비트 할당으로 구성된다. 일반적으로 비디오 시퀀스(Sequence)의 각 화면들은 서로 많은 상관성을 가지고 있다. 본 논문에서는 이러한 점을 고려하여, 다른 화면들의 화질에 상대적으로 더 많은 영향을 미칠 수 있는 중요한 화면을 선택하고, 선택된 화면들은 각각의 중요도에 따라 더 많은 비트가 할당되어 화질이 향상된다. 선택된 화면의 화질 향상은 이 화면으로부터 움직임 예측과 움직임 보상을 하는 다른 화면의 화질까지도 향상시킨다. 본 논문에서 제안된 방법은 MPEG-4비디오를 비롯하여 최근에 만들어진 H.264/AVC 부호화 표준에서도 좋은 결과를 보였다.