• Title/Summary/Keyword: Coded Signal

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Performance Enhancement of SBC for Voice Signal Using Adaptive Postfiltering at the Medium Bit Rate (중간 전송율에서 적응 포스트 필터링을 이용한 음성용 SBC의 성능 향상)

  • 김원구;이남걸;윤대희;차일환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.2
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    • pp.121-131
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    • 1992
  • In this paper, three methods are studied to enhance the performance of SBC ( Sub-Band Coding )schemes for voice signal at the medium bit rate between 12 kbps and If; kbps, and adaptive postfilteritng using human auditory characteristics Is (Bone at the decoder out put. First, GQMF(Generalized Quadrature Mirror Filter ) Is used instead of QME'((Quadrature MirrorFiltcr ) to have better performance. Second, by adaptive bit allocation to each sub-band, speech quality is enhanced and valuable rate ceding If possible. Third, corriparlson study oS thr: coder performance using APCM(Adaptive Pulse Code ModulatioTi) and ADPCM( Adaptive Differentiai Pulse Code Modulatiori) , Indicates that SB AfCM performance better than the other. Adaptive postfiltering at the decoder output enhances the quality of the coded speech. The two proposed postfiltering methods decrease the noise sufficiently at the expense of the low computational load.

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Signal Processing and Implementation of Transmitter for Cochlear Implant (인공 와우를 위한 신호 처리 및 전달부의 구현)

  • Chae, D.;Choi, D.;Byun, J.;Baeck, S.;Kong, H.;Park, S.
    • Proceedings of the KIEE Conference
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    • 1993.07a
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    • pp.284-286
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    • 1993
  • Software and hardware for cochlear implant system have been developed to create a speech signal processing system which, in real-time, extracts model parameter including formants, pitch, amplitude information. The system is based on the Texas Instruments TMS320 family. In hardware, computer interface has been desisted and implemented that allows presentation of biphasic pulse stimuli to patients with the hearing handicapped. The host computer sends a stream of bytes to the parallel port. Upon receipt of the data the interface generates the appropriate burst sequence that is delivered to the patient's external transmitter coil. The coded information is interpreted by the Nucleus-22 internal receiver that delivers the pulse to the specified electrodes at the specified amplitude and pulse width.

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A Class of Binary Cocyclic Quasi-Jacket Block Matrices

  • Lee Moon-Ho;Pokhrel Subash Shree;Choi Seung-Je;Kim Chang-Joo
    • Journal of electromagnetic engineering and science
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    • v.7 no.1
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    • pp.28-34
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    • 2007
  • In this paper, we present a quasi-Jacket block matrices over binary matrices which all are belong to a class of cocyclic matrices is the same as the Hadamard case and are useful in digital signal processing, CDMA, and coded modulation. Based on circular permutation matrix(CPM) cocyclic quasi block low-density matrix is introduced in this paper which is useful in coding theory. Additionally, we show that the fast algorithm of quasi-Jacket block matrix.

On the Gain of Component-Swapping Technique in LDPC-Coded MIMO-OFDM Systems (DVB-T2 16K LDPC 부호가 적용된 MIMO-OFDM 시스템에서의 성분 맞교환 기술 이득)

  • Jeon, Sung-Ho;Yim, Zung-Kon;Kyung, Il-Soo;Kim, Man-Sik
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2010.07a
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    • pp.164-167
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    • 2010
  • `신호 공간 다이버시티(Signal Space Diversity)'기술은 DVB-T2 표준에 포함된 기술로써, 추가적인 전력이나 대역폭의 희생없이 검파에 있어 성능 이득을 얻을 수 있어 DVB-T2 물리계층 핵심적인 기술 중 하나로 평가받으며, 후속 표준인 DVB-NGH 에도 적용 가능성이 높은 기술이다. 본 논문에서는 '신호 공간 다이버시티' 기술을 MIMO 시스템으로 확장하기 위해서 발생하는 문제점에 대해서 분석한 뒤, 이를 해결하기 위해 제안된 '성분 맞교환(Component-Swapping)' 기술을 현재 논의 중에 있는 DVB-NGH 시스템에 적용하여 주어진 실험 환경에서 2.2~3.0dB 가량의 이득을 가짐을 실험적으로 확인하였다.

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A Temporal Diversity using Vector Perturbation

  • Park, Jung-Yong;Shim, Byong-Hyo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2010.07a
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    • pp.64-66
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    • 2010
  • In this paper, we propose a temporal diversity scheme based on the vector perturbation for a multiuser multipleinput multiple-output (MIMO) broadcasting system. Our method is inspired by the fact that precoding process of the vector perturbation designed to suppress the multiuser interference causes a reduction of the transmitted signal power. In order to boost up the transmit power, we employ a non-integer based vector perturbation together with temporal transmit diversity. We show from the simulation on 10${\times}$10 multiuser MIMO system that the proposed method outperforms the epetition coded vector perturbation scheme as well as the standard vector perturbation.

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Compensation Algorithm of Arrival Time Mismatch in the Space-Time Coded Systems

  • Kim, Min-Hyuk;Choi, Suk-Soon;Jung, Ji-Won;Lee, Seong-Ro;Cho, Han-Na;Choi, Myeong-Soo
    • Journal of information and communication convergence engineering
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    • v.6 no.3
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    • pp.353-357
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    • 2008
  • One objective in developing the next generation of wireless communication systems is to increase data rates and reliability. A promising way to achieve this is to combine multiple-input and multiple-output signal processing with a space-time coding scheme, which offers higher coding and diversity gains and improves the spectrum efficiency and reliability of a wireless communication system. It is noted, however, that time delay differences and phase differences among different channels increase symbol interference and degrade system performance. In this letter, we investigate phase differences and their effects on multiple-input and multiple-output systems, and propose a compensation algorithm for the Rayleigh fading model to minimize their effects.

Digital Hearing Aids Specific $\mu$DSP Chip Design by Verilog HDL

  • Jarng, Soon-Suck;Chen, Lingfen;Kwon, You-Jung
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.190-195
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    • 2005
  • The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

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Performance Analysis on Error Correction Scheme for Wireless Sensor Network over Node-to-node Interference

  • Choi, Sang-Min;Moon, Byung-Hyun;Ryu, Jeong-Tak;Park, Se-Hyun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.1 no.2
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    • pp.37-42
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    • 2006
  • In this paper, we study a problem of providing reliable data transmission in wireless sensor network(WSN). A system with forward error correction9FEC) can provide an objective reliability while using less transmission power than a system without FEC. We propose the use of LDPC codes of various code rate (0.53, 0.81, 0.91) of FEC for WSN. Node-node-node interference is considered in the simulation in addition to AWGN in the channel. It is shown that the rate of 0.91 LDPC coded system obtained 7dB gain in signal to noise ratio over a system without FEC.

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Reduced-Resolution Intra Block Coding Mode

  • Park, Sung-Jae;Nam, Jung-Hak;Sim, Dong-Gyu;Oh, Seoung-Jun;Hong, Jin-Woo
    • ETRI Journal
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    • v.31 no.1
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    • pp.80-82
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    • 2009
  • In this letter, a new intra-block coding mode is presented to improve the coding efficiency for band-limited signals. A band-limited block is sub-sampled, and the sub-sampled signal is coded on the basis of the conventional prediction/transform coding. The rest of the samples are reconstructed by interpolation at the decoder side without any side information. Experimental results show that the proposed algorithm achieves coding gains of 2.7% for common intermediate format (CIF), 4.29% for quarter CIF, and 6.39% for 720p60 sequences against the H.264/AVC JM10.2 reference software.

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An Implementation Method of Cycle Accurate Simulator for the Design of a Pipelined DSP

  • Park, Hyeong-Bae;Park, Ju-Sung;Kim, Tae-Hoon;Chi, Hua-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.4
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    • pp.246-251
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    • 2006
  • In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.