• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• International Journal of Naval Architecture and Ocean Engineering
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• v.10 no.4
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• pp.491-498
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• 2018

The cost evaluation for voyage route planning in an ice-covered sea is one of the major topics among ship owners. Information of the ice properties, such as ice type, concentration of ice, ice thickness, strength of ice, and speed-power relation under ice conditions are important for determining the optimal route in ice and low operational cost perspective. To determine achievable speed at any designated pack ice condition, a model test of resistance, self-propulsion, and overload test in ice and ice-free water were carried out in a KRISO ice tank and towing tank. The available net thrust for ice and an estimation of the ice resistance under any pack ice condition were also performed by I-RES. The in-house code called 'I-RES', which is an ice resistance estimation tool that applies an empirical formula, was modified for the pack ice module in this study. Careful observations of underwater videos of the ice model test made it possible to understand the physical phenomena of underneath of the hull bottom surface and determine the coverage of buoyancy. The clearing resistance of ice can be calculated by subtracting the buoyance and open water resistance form the pre-sawn ice resistance. The model test results in pack ice were compared with the calculation results to obtain a correlation factor among the pack ice resistance, ice concentration, and ship speed. The resulting correlation factors were applied to the calculation results to determine the pack ice resistance under any pack ice condition. The pack ice resistance under the arbitrary pack ice condition could be estimated because software I-RES could control all the ice properties. The available net thrust in ice, which is the over thrust that overcomes the pack ice resistance, will change the speed of a ship according to the bollard pull test results and thruster characteristics (engine & propulsion combination). The attainable speed at a certain ice concentration of pack ice was determined using the interpolation method. This paper reports a procedure to determine the attainable speed in pack ice and the sample calculation using the Araon vessel was performed to confirm the entire process. A more detailed description of the determination of the attainable speed is described. The attainable speed in 1.0 m, 90% pack ice and 540 kPa strength was 13.3 knots.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.111-121
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• 2014

In this paper, we propose tree-based hybrid query tree architecture utilizing time slot. 4-Bit Pattern Slot Allocation(4-SL) has a 8-ary tree structure and when tag ID responses according to query of the reader, it applies a digital coding method, the Manchester code, in order to extract the location and the number of collided bits. Also, this algorithm can recognize multiple Tags by single query using 4 fixed time slots. The architecture allows the reader to identify 8 tags at the same time by responding 4 time slots utilizing the first bit($[prefix+1]^{th}$, F ${\in}$ {'0' or '1'}) and bit pattern from second ~ third bits($[prefix+2]^{th}{\sim}[prefix+3]^{th}$, $B_2{\in}$ {"00" or "11"}, $B_1{\in}$ {"01" or "10"}) in tag ID. we analyze worst case of the number of query nodes(prefix) in algorithm to extract delay time for recognizing multiple tags. The identification delay time of the proposed algorithm was based on the number of query-responses and query bits, and was calculated by each algorithm.

• Journal of the Korea Society for Simulation
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• v.16 no.2
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• pp.27-35
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• 2007

When sensor networks are deployed in open environments, all the sensor nodes are vulnerable to physical threat. An attacker can physically capture a sensor node and obtain the security information including the keys used for data authentication. An attacker can easily inject false reports into the sensor network through the compromised node. False report can lead to not only false alarms but also the depletion of limited energy resource in battery powered sensor networks. To overcome this threat, Fan Ye et al. proposed that statistical on-route filtering scheme(SEF) can do verify the false report during the forwarding process. In this scheme, the choice of a security threshold value is important since it trades off detection power and energy, where security threshold value is the number of message authentication code for verification of false report. In this paper, we propose a fuzzy rule-based system for security threshold determination that can conserve energy, while it provides sufficient detection power in the SEF based sensor networks. The fuzzy logic determines a security threshold by considering the probability of a node having non-compromised keys, the number of compromised partitions, and the remaining energy of nodes. The fuzzy based threshold value can conserve energy, while it provides sufficient detection power.

• Korean Journal of Environmental Agriculture
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• v.28 no.3
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• pp.310-325
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• 2009

Veterinary drugs have been used to prevent livestock diseases for many years. In spite of having advantages, sometimes indiscriminate application, overdose and abuse may cause risk for human. Therefore, management and risk assessment of veterinary drugs become essential to ensure food safety. So the National Veterinary Research & Quarantine Service (NVRQS) impose on registration for use of veterinary drugs also Korea Food and Drug Administration (KFDA) fixed the maximum residue limits (MRLs) for veterinary drugs in food. Basically, KFDA set MRLs based on the veterinary drugs residual data. Moreover, KFDA estimates the theoretical maximum daily intake (TMDI) with food consumption data and population mean body weight. Recently, 116 veterinary drug MRLs including banned veterinary drugs have been established and other 32 veterinary drugs MRLs will be established within 2009. In 2010, MRLs among antibiotics and synthetic antibacterial agents in livestock fishery products (including milk and eggs) and honey (including royal jelly and propolis) which have not been set in Korea Food Code and Codex Alimentarius Commission (CAC) will be regulated as uniform limit (0.03 mg/kg). In future, veterinary drugs will be controlled strictly to strengthen public health by improving analytical method.

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.4
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• pp.368-375
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• 2013

Failure of small bore piping welds is a recurring problem at nuclear power plants. And the socket weld cracking in small bore piping has caused unplanned plant shutdowns for repair and high economic impact on the plants. Consequently, early crack detection, including the detection of manufacturing defects, is of the utmost importance. Until now, the surface inspection methods has been applied according to ASME Section XI requirements. But the ultrasonic inspection as a volumetric method is also applying to enforce the inspection requirement. However, the conventional manual ultrasonic inspection techniques are used to detect service induced fatigue cracks. And there was uncertainty on manual ultrasonic inspection because of limited access to the welds and difficulties with contact between the ultrasonic probe and the OD(outer diameter) surface of small bore piping. In this study, phased array ultrasonic inspection technique is applied to increase inspection speed and reliability. To achieve this object, the 3.5 MHz phased array ultrasonic transducer are designed and fabricated. The manually encoded scanner was also developed to enhance contact conditions and maintain constant signal quality. Additionally inspection system is configured and inspection procedure is developed.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.15 no.2
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• pp.104-113
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• 2005

A variety of ergonomic assessment methods of lifting tasks known as a major cause of work-related lower back pain have been used. But there is a limited information in choosing the most appropriate assessment method for a particular job and in finding out strengths and weakness of the methods. The purpose of this study was to assess and compare the ergonomic risks of lifting tasks in a marine diesel engine production industry by three lifting ergonomic assessment tools widely used: the National Institute for Occupational Safety and Health(NIOSH) Revised Lifting Equation(NLE), the Washington Administrative Code 296-62-0517(WAC), and the Snook Tables. Lifting index(weight of load/Recommended Weight Limit) of NLE($LI_{NLE}$) was above 1 at 34 tasks(75.6%) of a total number of 45 lifting tasks. LI of WAC($LI_{WAC}$) was above 1 at 11 tasks(24.4 %). LI of Snook Table($LI_{Snook}$) was above 1 at 29 tasks(64.4%). Thus, LI was high in orders of $LI_{NLE}$ > $LI_{Snook}$ > $LI_{WAC}$. There were significantly high correlations among three Lls(p<0.01). The correlation coefficients between $LI_{NLE}$and the other three Lls($LI_{WAC}$ and $LI_{Snook}$) were r=0.93 and r=0.88, respectively. The linear regression equations were y = 0.444x + 0.11(r=0.93) between $LI_{NLE}$ and $LI_{WAC}$, y = 0.93x + 0.008(r=0.88) between LI(NLE) and $LI_{Snook}$. The LI values by WAC was significantly lower than those by the other tools. The compared features, strength and limitation among these tools were described in this paper.

• Journal of Technology Innovation
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• v.21 no.1
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• pp.141-163
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• 2013

As the importance of biotechnology has been increased as a growth engine for country, most countries get focused on securing technological competitiveness in the field of biotechnology. Under the fierce global competition, it is very important to identify technological competitiveness of Korea and our neighboring countries in order to carry out effective research and development. Expert opinion survey such as Delphi is mainly conducted to analyze the technological competitiveness, but the method based on experts' intuition may produce different results depending on survey respondents due to the strong subjective inclination. In this study, the patent registered in US was utilized to analyze the technological competitiveness based on objective data. Targeting countries were Korea, China and Japan which were leading nations in the Northeast Asia. As analytical indexes, NP(Number of Patents), CPP(Cites per Patent), PII(Patent Impact Index), TS(Technology Strength), TI(Technology Independence), PFS(Patent Family Size) were used for analysis. Moreover, the industrial linkage with biotechnology was analyzed by matching IPC code of patents with 44 industries. Based on this analysis, technological convergence and utilization were quantified. The findings can be utilized as basic data when policy is established to improve technological competitiveness in the field of biotechnology.

• Journal of the Korea Concrete Institute
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• v.25 no.5
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• pp.497-508
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• 2013

This paper introduces a numerical model which can evaluate the fire-resistant capacity of reinforced concrete members. On the basis of the transient heat transfer considering the heat conduction, convection and radiation, time-dependent temperature distribution across a section is determined. A layered fiber section method is adopted to consider non-linear material properties depending on the temperature and varying with the position of a fiber. Furthermore, effects of non-mechanical strains of each fiber like thermal expansion, transient strain and creep strain are reflected on the non-linear structural analysis to take into account the extreme temperature variation induced by the fire. Analysis results by the numerical model are compared with experimental data from the standard fire tests to validate an exactness of the introduced numerical model. Also, time-dependent changes in the resisting capacities of reinforced concrete members exposed to fire are investigated through the analyses and, the resisting capacities evaluated are compared with those determined by the design code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.