• Title/Summary/Keyword: Code Generation Tools

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A Design of Constructing Diagram Repository for UML Diagram Tools (UML 다이어그램 도구를 위한 다이어그램 정보의 구축과 설계)

  • Kim, Yun-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.2
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    • pp.244-251
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    • 2020
  • This paper presents a design of the Meta-Class Repository (MCR) which maintain syntactically analyzed and structured meta-class information from UML diagrams, and then proposes 'meta-class,' also known as super-class, to construct structured information analyzed syntactically. The MCR is a collection of these meta-classes which contains the information extracted from diagrams. This paper also presents a design of the Code Generation Engine (CGE) which roles generating codes corresponding classes from UML diagrams based on the MCR maintaining a collection of meta-classes which is syntactically-analyzed and constructed in previous process. The logics of CGE are designed to generate codes collaborated with MCR and CGE with integration. The logics of CGE mechanism is presented with the form of finite state machine to present the algorithms of code generation formally and have the advantages of simplicity and easiness in development.

Formal Description and Reference Implementation Code Generation for a Security Algorithm using VDM-SL (VDM-SL을 이용한 보안 알고리즘의 형식적 표현과 참조구현 코드 생성)

  • Kim, Young-Gil;Kim, Ki-Su;Kim, Young-Wha;Ryou, Jae-Cheol;Jang, Chung-Ryong
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.6 no.4
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    • pp.67-84
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    • 1996
  • VDL-SL (Vienna Development Method-Specification Language) is one of the FSL(Formal Specification Language) which is being presented for the correct description of the security relevant standards. Several tools are being developed for the correctness and the convenience in the description and executable code generation of security relevant standards using VDM-SL. The IFAD VDM-SL Toolbox is one that has many functions : syntax checking, type checking, c++ code generation, test coverage information. This paper describes a formal method for description and implementation of MD4 algorithm using VDM-SL and IFAD VDM-SL Toolbox, and examines the result applied to secure hash algorithm, and proposes the relation to strict conformance test which recently suggested as a security test method.

AIT: A method for operating system kernel function call graph generation with a virtualization technique

  • Jiao, Longlong;Luo, Senlin;Liu, Wangtong;Pan, Limin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.5
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    • pp.2084-2100
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    • 2020
  • Operating system (OS) kernel function call graphs have been widely used in OS analysis and defense. However, most existing methods and tools for generating function call graphs are designed for application programs, and cannot be used for generating OS kernel function call graphs. This paper proposes a virtualization-based call graph generation method called Acquire in Trap (AIT). When target kernel functions are called, AIT dynamically initiates a system trap with the help of a virtualization technique. It then analyzes and records the calling relationships for trap handling by traversing the kernel stacks and the code space. Our experimental results show that the proposed method is feasible for both Linux and Windows OSs, including 32 and 64-bit versions, with high recall and precision rates. AIT is independent of the source code, compiler and OS kernel architecture, and is a universal method for generating OS kernel function call graphs.

An Optimal ILP Algorithm of Memory Access Variable Storage for DSP in Embedded System (임베디드 시스템에서 DSP를 위한 메모리 접근 변수 저장의 최적화 ILP 알고리즘)

  • Chang, Jeong-Uk;Lin, Chi-Ho
    • KIPS Transactions on Computer and Communication Systems
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    • v.2 no.2
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    • pp.59-66
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    • 2013
  • In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

Development of smart CAD/CAM system for machining center based on B-Rep solid modeling techniques(l) (A study on the B-Rep solid modeler using half edge data structure) (B-Rep 솔리드모델을 이용한 머시닝센터용 CAD/CAM시스템 개발(I))

  • Yang, Hee-Goo;Kim, Seok-Il
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.3
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    • pp.150-157
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    • 1996
  • In this paper, to develop a smart CAD/CAM system for systematically performing from the 3-D solid shape design of products to the CNC cutting operation of products by a machining center, a B-Rep solid modeler is realized based on the half edge data structure. Because the B-Rep solid modeler has the various capabilities related to the solid definition functions such as the creation operation of primitives and the translational and rotational sweep operation, the solid manipulation functions such as the split operation and the Boolean set operation, and the solid inversion function for effectively using the data structure, the 3-D solid shape of products can be easily designed and constructed. Also, besides the automatic generation of CNC code, the B-Rep solid modeler can be used as a powerful tool for realizing the automatic generation of finite elements, the interfer- ence check between solids, the structural design of machine tools and robots and so on.

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A Study on Object-Oriented Programming Education using Visualization Method (시각화방법을 이용한 객체지향프로그래밍 교육에 관한 연구)

  • Shin, Woochang
    • Journal of The Korean Association of Information Education
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    • v.21 no.5
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    • pp.557-565
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    • 2017
  • In the era of the Fourth Industrial Revolution, programming education is becoming more important. However, it takes a lot of time and practice for students to acquire programming skills. In particular, students find it more difficult to learn object-oriented languages such as JAVA and C++, which are widely used in the industrial field. In this paper, we propose a visualization method of object interaction that can help to educate the concept of object-oriented programming, understand functions, and improve source code analysis and understanding. The proposed visualization method automatically changes the existing source code and visualizes the operation of the objects simultaneously with the execution of the program.

SARAPAN-A Simulated-Annealing-Based Tool to Generate Random Patterned-Channel-Age in CANDU Fuel Management Analyses

  • Kastanya, Doddy
    • Nuclear Engineering and Technology
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    • v.49 no.1
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    • pp.267-276
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    • 2017
  • In any reactor physics analysis, the instantaneous power distribution in the core can be calculated when the actual bundle-wise burnup distribution is known. Considering the fact that CANDU (Canada Deuterium Uranium) utilizes on-power refueling to compensate for the reduction of reactivity due to fuel burnup, in the CANDU fuel management analysis, snapshots of power and burnup distributions can be obtained by simulating and tracking the reactor operation over an extended period using various tools such as the $^*SIMULATE$ module of the Reactor Fueling Simulation Program (RFSP) code. However, for some studies, such as an evaluation of a conceptual design of a next-generation CANDU reactor, the preferred approach to obtain a snapshot of the power distribution in the core is based on the patterned-channel-age model implemented in the $^*INSTANTAN$ module of the RFSP code. The objective of this approach is to obtain a representative snapshot of core conditions quickly. At present, such patterns could be generated by using a program called RANDIS, which is implemented within the $^*INSTANTAN$ module. In this work, we present an alternative approach to derive the patterned-channel-age model where a simulated-annealing-based algorithm is used to find such patterns, which produce reasonable power distributions.

STATUS AND PERSPECTIVE OF TWO-PHASE FLOW MODELLING IN THE NEPTUNE MULTISCALE THERMAL-HYDRAULIC PLATFORM FOR NUCLEAR REACTOR SIMULATION

  • BESTION DOMINIQUE;GUELFI ANTOINE;DEN/EER/SSTH CEA-GRENOBLE,
    • Nuclear Engineering and Technology
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    • v.37 no.6
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    • pp.511-524
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    • 2005
  • Thermalhydraulic reactor simulation of tomorrow will require a new generation of codes combining at least three scales, the CFD scale in open medium, the component scale and the system scale. DNS will be used as a support for modelling more macroscopic models. NEPTUNE is such a new generation multi-scale platform developed jointly by CEA-DEN and EDF-R&D and also supported by IRSN and FRAMATOME-ANP. The major steps towards the next generation lie in new physical models and improved numerical methods. This paper presents the advances obtained so far in physical modelling for each scale. Macroscopic models of system and component scales include multi-field modelling, transport of interfacial area, and turbulence modelling. Two-phase CFD or CMFD was first applied to boiling bubbly flow for departure from nucleate boiling investigations and to stratified flow for pressurised thermal shock investigations. The main challenges of the project are presented, some selected results are shown for each scale, and the perspectives for future are also drawn. Direct Numerical Simulation tools with Interface Tracking Techniques are also developed for even smaller scale investigations leading to a better understanding of basic physical processes and allowing the development of closure relations for macroscopic and CFD models.

Stacked Autoencoder Based Malware Feature Refinement Technology Research (Stacked Autoencoder 기반 악성코드 Feature 정제 기술 연구)

  • Kim, Hong-bi;Lee, Tae-jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.30 no.4
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    • pp.593-603
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    • 2020
  • The advent of malicious code has increased exponentially due to the spread of malicious code generation tools in accordance with the development of the network, but there is a limit to the response through existing malicious code detection methods. According to this situation, a machine learning-based malicious code detection method is evolving, and in this paper, the feature of data is extracted from the PE header for machine-learning-based malicious code detection, and then it is used to automate the malware through autoencoder. Research on how to extract the indicated features and feature importance. In this paper, 549 features composed of information such as DLL/API that can be identified from PE files that are commonly used in malware analysis are extracted, and autoencoder is used through the extracted features to improve the performance of malware detection in machine learning. It was proved to be successful in providing excellent accuracy and reducing the processing time by 2 times by effectively extracting the features of the data by compressively storing the data. The test results have been shown to be useful for classifying malware groups, and in the future, a classifier such as SVM will be introduced to continue research for more accurate malware detection.

A New Integrated Software Development Environment Based on SDL, MSC, and CHILL for Large-scale Switching Systems

  • Lee, Dong-Gill;Lee, Joon-Kyung;Choi, Wan;Lee, Byung-Sun;Han, Chi-Moon
    • ETRI Journal
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    • v.18 no.4
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    • pp.265-286
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    • 1997
  • This paper presents a new software development environment that supports an integrated methodology for covering all phases of software development and gives integrated methods with tools for ITUT (Telecommunication Standardization Section of the International Telecommunication Union) languages. The design of the environment to improve software productivity and quality is based on five main concepts: 1) formal specifications based on SDL (Specification and Description Language) and MSC (Message Sequence Charts) in the design phase, 2) verification and validation of those designs by tools, 3) automatic code generation and a safe separate compilation scheme based on CHILL (CCITT High-Level Language) to facilitate programming-in-the-many and programming-in-the-large. 4) debugging of distributed real-time concurrent CHILL programs, and 5) simulation of application software for integrated testing on the host machine based on CHILL. The application results of the environment compared with other approaches show that the productivity is increased by 19 % because of decreasing implementation and testing cost, and the quality is increased by 83 % because of the formal specifications with its static and dynamic checking facilities.

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