• Journal of the Korean institute of surface engineering
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• v.35 no.6
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.6
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• pp.1056-1063
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• 2006

Thermal evaporated 10 nm-Ni/l nm-Ir/(or polycrystalline)p-Si(100) and 10 nm-$Ni_{50}Co_{50}$/(or polycrystalline)p-Si(100) films were thermally annealed using rapid thermal annealing fur 40 sec at $300{\sim}1200^{\circ}C$. The annealed bilayer structure developed into Ni(Ir or Co)Si and resulting changes in sheet resistance, microstructure, phase and composition were investigated using a four-point probe, a scanning electron microscopy, a field ion beam, an X-ray diffractometer and an Auger electron spectroscope. The final thickness of Ir- and Co-inserted nickel silicides on single crystal silicon was approximately 20$\sim$40 nm and maintained its sheet resistance below 20 $\Omega$/sq. after the silicidation annealing at $1000^{\circ}C$. The ones on polysilicon had thickness of 20$\sim$55 nm and remained low resistance up to $850^{\circ}C$. A possible reason fur the improved thermal stability of the silicides formed on single crystal silicon substrate is the role of Ir and Co in preventing $NiSi_2$ transformation. Ir and Co also improved thermal stability of silicides formed on polysilicon substrate, but this enhancement was lessened due to the formation of high resistant phases and also a result of silicon mixing during high temperature diffusion. Ir-inserted nickel silicides showed surface roughness below 3 nm, which is appropriate for nano process. In conclusion, the proposed Ir- and Co- inserted nickel silicides may be superior over the conventional nickel monosilicides due to improved thermal stability.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.208-213
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• 1998

Silicidation of the Co/Ti/Si bilayer system in which Ti is used as epitaxy promoter for $CoSi_2$has recently received much attention. The Co/Ti bilayer on the spacer oxide of gate electrode must be thermally stable at high temperatures for a salicide transistor to be fabricated successfully. In the $SiO_2$substrate was rapid-thermal annealed. The Sheet resistances of the Co/Ti bilayer increased substantially after annealing at $600^{\circ}C$, which is due to the agglomeration of the Co layer to reduce the interface energy between the Co layer and the $SiO_2$substrate. In the bilayer system insulating Ti oxide stoichiometric Ti oxide and silicide were not found after annealing.

• Korean Journal of Materials Research
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• v.8 no.9
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• pp.791-796
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• 1998

self-aligned silicide(salicide)제조시 CoSi2의 에피텍셜 성장을 돕기 위하여 Co와 Si 사이에 내열금속층을 넣은 Co/내열금속/Si의 실리사이드화가 관심을 끌고 있다. Hf 역시 Ti와 마찬가지로 이러한 용도로 사용될 수 있다. 한편, Co/Hf 이중층 salicide 트랜지스터가 성공적으로 만들어지기 위해서는 spacer oxide 위에 증착된 Co/Hf 이중층이 열적으로 안정해야 한다. 이러한 배경에서 본 연구에서는 SiO2기판 위에 증착한 Co 단일층과 Co/Hf 이중층을 급속열처리할 때 Co와 SiO2간의 계면과 Co/Hf와 SiO2간의 계면에서의 상호반응에 대하여 조사하였다. Co 단일층과 Co/Hf 이중층은 각각 $500^{\circ}C$와 $550^{\circ}C$에서 열처리한 후 면저항이 급격하게 증가하기 시작하였는데, 이것은 Co층이 SiO2와의 계면에너지를 줄이기 위하여 응집되기 때문이다. 이 때 Co/Hf의 경우 열처리후 Hf에 의하여 SiO2 기판이 일부 분해됨으로써 Hf 산화물이 형성되었으나, 전도성이 있는 HfSix 등의 화합물은 발견되지 않았다.

• Korean Journal of Materials Research
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• v.4 no.1
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• pp.9-23
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• 1994

Epitaxial $CoSi_2$ layer has been grown on NaCl(100) substrate at low deposition temperature($200^{\circ}C$) by multitarget bias cosputter deposition(MBCD). The phase sequence and crystallinity of deposited silicide as a function of deposition temperature and substrate bias voltage were studied by X-ray diffraction(XRD) and transmission electron microscopy(TEM) analysis. Crystalline Si was grown at $200^{\circ}C$ by metal induced crystallization(M1C) and self bias effect. In addition to, the MIC was analyzed both theoretically and experimentally. The observed phase sequence was $Co_2Si \to CoSi \to Cosi_2$ and was in good agreement with that predicted by effective heat of formation rule. The phase sequence, the CoSi(l11) preferred orientation, and the crystallinity had stronger dependence on the substrate bias voltage than the deposition temperature due to the collisional cascade mixing, the in-situ cleaning, and the increase in the number of nucleation sites by ion bombardment of growing surface. Grain growth induced by ion bombardment was observed with increasing substrate bias voltage at $200^{\circ}C$ and was interpreted with ion bombardment dissociation model. The parameters of $E_{Ar}\;and \alpha(V_s)$ were chosen to properly quantify the ion bombardment effect on the variation in crystallinty at $200^{\circ}C$ with increasing substrate bias voltage using Langmuir probe.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.13-17
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• 2007

Effect of Co substitution on crystal structures of two nickel silicides, NiSi and $NiSi_2$, is investigated by using an ab initio calculation. Relaxed NiSi and $NiSi_2$ structures are calculated and the calculated lattice parameters are in good agreement with experimentally determined lattice parameters within about 2%. A Co atom substitutes a Ni and Si site, respectively, to evaluate the preferable site between them. Co prefers Ni site to Si site in both NiSi and $NiSi_2$. The calculated total energy also indicates that the Co substitution to Ni site stabilizes both the NiSi and $NiSi_2$ structures. Co also prefers Ni site in $NiSi_2$ to that in NiSi, indicating that $NiSi_2$ becomes more stable than NiSi with Co substitution. As Co addition to NiSi improves its thermal stability experimentally, this indicates that the energy barrier between the two phases is high enough to prevent the phase transformation from NiSi to $NiSi_2$ up to high temperature.

• Korean Journal of Materials Research
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• v.7 no.7
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• pp.587-591
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• 1997

RBS와 XRD를 이용하여 C o-Nb이중층 실리사이드와 구리 배선층간의 열적안정성에 관하여 조사하였다. Cu$_{3}$Si등의 구리 실리사이드는 열처리시 40$0^{\circ}C$정도에서 처음 형성되기 시작하였는데, 이 때 형성되는 구리 실리사이드는 기판의 상부에 존재하던 준안정한 CoSi의 분해시에 발생한 Si원자와의 반응에 의한 것이다. 한편, $600^{\circ}C$에서의 열처리 후에는 CoSi$_{2}$층을 확산.통과한 Cu원자와 기판 Si와의 반응에 의하여 CoSi$_{2}$/Si계면에도 구리 실리사이드가 성장하였는데, 이렇게 구리 실리사이드가 CoSi$_{2}$/Si 계면에 형성되는 것은 Cu원자의 확산속도가 여러 중간층에서 Si 원자의 확산속도 보다 더 빠르기 때문이다. 열처리 결과 최종적으로 얻어진 층구조는 CuNbO$_{3}$/Cu$_{3}$Si/Co-Nb합금층/Nb$_{2}$O$_{5}$CoSi$_{2}$/Cu$_{3}$Si/Si이었다. 여기서 상부에 형성된 CuNbO$_{3}$는 Cu원자가 Nb$_{2}$O$_{5}$및 Co-Nb합금층과 반응하여 기지조직의 입계에 석출되어 형성된 것이다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.671-674
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• 2003

본 논문에서는 Cobalt interlayer 와 Titanium Nitride(TiN) capping layer를 Ni SALICIDE의 단점인 열 안정성과 sheet resistance 와 series 저항을 감소시키는데 적용하여 0.lum 급 CMOS 소자의 특성을 연구하였다. 첫째로, Ni/Si 의 interface 에 Co interlayer 를 증착하여 Nickel Silicide의 단점인 열 안정성 평가인 700℃, 30min의 furnace annealing 후에 낮은 sheet resistance와 누설전류를 줄일 수 있었다. 두번째로, TiN caping layer를 적용하여 실리사이드 형성시 산소와의 반응을 막아 실리사이드의 표면특성을 향상시켜 누설전류의 특성을 개선하였다. 결과적으로 소자의 구동전류 향상, 누설전류 저하, 낮은 면저항으로 소자의 특성을 개선하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.68-76
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• 1992

Concurrent Junction process (simultaneous formation of a silicide and a junction on the implanted substrate) by Rapid Thermal Annealig has been investigated. Electrical and material properties of CoSi$_2$ films were analyzed with Alpha Step, 4-point probe, X-ray diffraction(XRD) and Scanning Electron Microscope(SEM). And CoSi$_2$ junctions were examined with Spreading Resistance probe in order to see the redistribution of electrically activated dopants and determined the junction depth. Two step annealing process, which was 80$0^{\circ}C$ for 30sec and 100$0^{\circ}C$ for 30sec in NS12T ambient was employed to form CoSi$_2$ and shallow junctions. Resistivity of CoSi$_2$ was turned out to be 11-15${\mu}$cm and shallow junctions less than 0.1$\mu$m were successfully formed by the process. It was found that the dopant concentration at CoSi$_2$/Si interface increased as decreasing the thickness of Co films in case of $p^{+}/n$ and $n^{+}/p$ junctions while the junction depth decreased as increasing CoSiS12T thickness in case of $p^{+}/n$ junction.